1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_mailbox.h" 14 #include "socfpga_reset_manager.h" 15 #include "socfpga_sip_svc.h" 16 17 18 /* Total buffer the driver can hold */ 19 #define FPGA_CONFIG_BUFFER_SIZE 4 20 21 static int current_block, current_buffer; 22 static int read_block, max_blocks, is_partial_reconfig; 23 static uint32_t send_id, rcv_id; 24 static uint32_t bytes_per_block, blocks_submitted; 25 26 27 /* SiP Service UUID */ 28 DEFINE_SVC_UUID2(intl_svc_uid, 29 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 30 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 31 32 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 33 uint64_t x1, 34 uint64_t x2, 35 uint64_t x3, 36 uint64_t x4, 37 void *cookie, 38 void *handle, 39 uint64_t flags) 40 { 41 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 42 SMC_RET1(handle, SMC_UNK); 43 } 44 45 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 46 47 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 48 { 49 uint32_t args[3]; 50 51 while (max_blocks > 0 && buffer->size > buffer->size_written) { 52 args[0] = (1<<8); 53 args[1] = buffer->addr + buffer->size_written; 54 if (buffer->size - buffer->size_written <= bytes_per_block) { 55 args[2] = buffer->size - buffer->size_written; 56 current_buffer++; 57 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 58 } else 59 args[2] = bytes_per_block; 60 61 buffer->size_written += args[2]; 62 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 63 3U, CMD_INDIRECT); 64 65 buffer->subblocks_sent++; 66 max_blocks--; 67 } 68 69 return !max_blocks; 70 } 71 72 static int intel_fpga_sdm_write_all(void) 73 { 74 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 75 if (intel_fpga_sdm_write_buffer( 76 &fpga_config_buffers[current_buffer])) 77 break; 78 return 0; 79 } 80 81 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) 82 { 83 uint32_t ret; 84 85 if (query_type == 1) 86 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false); 87 else 88 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); 89 90 if (ret) { 91 if (ret == MBOX_CFGSTAT_STATE_CONFIG) 92 return INTEL_SIP_SMC_STATUS_BUSY; 93 else 94 return INTEL_SIP_SMC_STATUS_ERROR; 95 } 96 97 if (query_type != 1) { 98 /* full reconfiguration */ 99 if (!is_partial_reconfig) 100 socfpga_bridges_enable(); /* Enable bridge */ 101 } 102 103 return INTEL_SIP_SMC_STATUS_OK; 104 } 105 106 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 107 { 108 int i; 109 110 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 111 if (fpga_config_buffers[i].block_number == current_block) { 112 fpga_config_buffers[i].subblocks_sent--; 113 if (fpga_config_buffers[i].subblocks_sent == 0 114 && fpga_config_buffers[i].size <= 115 fpga_config_buffers[i].size_written) { 116 fpga_config_buffers[i].write_requested = 0; 117 current_block++; 118 *buffer_addr_completed = 119 fpga_config_buffers[i].addr; 120 return 0; 121 } 122 } 123 } 124 125 return -1; 126 } 127 128 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 129 uint32_t *count, uint32_t *job_id) 130 { 131 uint32_t resp[5]; 132 unsigned int resp_len = ARRAY_SIZE(resp); 133 int status = INTEL_SIP_SMC_STATUS_OK; 134 int all_completed = 1; 135 *count = 0; 136 137 while (*count < 3) { 138 139 status = mailbox_read_response(job_id, 140 resp, &resp_len); 141 142 if (resp_len < 0) 143 break; 144 145 max_blocks++; 146 147 if (mark_last_buffer_xfer_completed( 148 &completed_addr[*count]) == 0) 149 *count = *count + 1; 150 else 151 break; 152 } 153 154 if (*count <= 0) { 155 if (resp_len != MBOX_NO_RESPONSE && 156 resp_len != MBOX_TIMEOUT && resp_len != 0) { 157 mailbox_clear_response(); 158 return INTEL_SIP_SMC_STATUS_ERROR; 159 } 160 161 *count = 0; 162 } 163 164 intel_fpga_sdm_write_all(); 165 166 if (*count > 0) 167 status = INTEL_SIP_SMC_STATUS_OK; 168 else if (*count == 0) 169 status = INTEL_SIP_SMC_STATUS_BUSY; 170 171 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 172 if (fpga_config_buffers[i].write_requested != 0) { 173 all_completed = 0; 174 break; 175 } 176 } 177 178 if (all_completed == 1) 179 return INTEL_SIP_SMC_STATUS_OK; 180 181 return status; 182 } 183 184 static int intel_fpga_config_start(uint32_t config_type) 185 { 186 uint32_t argument = 0x1; 187 uint32_t response[3]; 188 int status = 0; 189 unsigned int size = 0; 190 unsigned int resp_len = ARRAY_SIZE(response); 191 192 is_partial_reconfig = config_type; 193 194 mailbox_clear_response(); 195 196 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 197 CMD_CASUAL, NULL, NULL); 198 199 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 200 CMD_CASUAL, response, &resp_len); 201 202 if (status < 0) 203 return status; 204 205 max_blocks = response[0]; 206 bytes_per_block = response[1]; 207 208 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 209 fpga_config_buffers[i].size = 0; 210 fpga_config_buffers[i].size_written = 0; 211 fpga_config_buffers[i].addr = 0; 212 fpga_config_buffers[i].write_requested = 0; 213 fpga_config_buffers[i].block_number = 0; 214 fpga_config_buffers[i].subblocks_sent = 0; 215 } 216 217 blocks_submitted = 0; 218 current_block = 0; 219 read_block = 0; 220 current_buffer = 0; 221 222 /* full reconfiguration */ 223 if (!is_partial_reconfig) { 224 /* Disable bridge */ 225 socfpga_bridges_disable(); 226 } 227 228 return 0; 229 } 230 231 static bool is_fpga_config_buffer_full(void) 232 { 233 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 234 if (!fpga_config_buffers[i].write_requested) 235 return false; 236 return true; 237 } 238 239 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 240 { 241 if (!addr && !size) { 242 return true; 243 } 244 if (size > (UINT64_MAX - addr)) 245 return false; 246 if (addr < BL31_LIMIT) 247 return false; 248 if (addr + size > DRAM_BASE + DRAM_SIZE) 249 return false; 250 251 return true; 252 } 253 254 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 255 { 256 int i; 257 258 intel_fpga_sdm_write_all(); 259 260 if (!is_address_in_ddr_range(mem, size) || 261 is_fpga_config_buffer_full()) 262 return INTEL_SIP_SMC_STATUS_REJECTED; 263 264 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 265 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 266 267 if (!fpga_config_buffers[j].write_requested) { 268 fpga_config_buffers[j].addr = mem; 269 fpga_config_buffers[j].size = size; 270 fpga_config_buffers[j].size_written = 0; 271 fpga_config_buffers[j].write_requested = 1; 272 fpga_config_buffers[j].block_number = 273 blocks_submitted++; 274 fpga_config_buffers[j].subblocks_sent = 0; 275 break; 276 } 277 } 278 279 if (is_fpga_config_buffer_full()) 280 return INTEL_SIP_SMC_STATUS_BUSY; 281 282 return INTEL_SIP_SMC_STATUS_OK; 283 } 284 285 static int is_out_of_sec_range(uint64_t reg_addr) 286 { 287 switch (reg_addr) { 288 case(0xF8011100): /* ECCCTRL1 */ 289 case(0xF8011104): /* ECCCTRL2 */ 290 case(0xF8011110): /* ERRINTEN */ 291 case(0xF8011114): /* ERRINTENS */ 292 case(0xF8011118): /* ERRINTENR */ 293 case(0xF801111C): /* INTMODE */ 294 case(0xF8011120): /* INTSTAT */ 295 case(0xF8011124): /* DIAGINTTEST */ 296 case(0xF801112C): /* DERRADDRA */ 297 case(0xFFD12028): /* SDMMCGRP_CTRL */ 298 case(0xFFD12044): /* EMAC0 */ 299 case(0xFFD12048): /* EMAC1 */ 300 case(0xFFD1204C): /* EMAC2 */ 301 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 302 case(0xFFD12094): /* ECC_INT_MASK_SET */ 303 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 304 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 305 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 306 case(0xFFD120C0): /* NOC_TIMEOUT */ 307 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 308 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 309 case(0xFFD120D0): /* NOC_IDLEACK */ 310 case(0xFFD120D4): /* NOC_IDLESTATUS */ 311 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 312 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 313 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 314 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 315 return 0; 316 317 default: 318 break; 319 } 320 321 return -1; 322 } 323 324 /* Secure register access */ 325 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 326 { 327 if (is_out_of_sec_range(reg_addr)) 328 return INTEL_SIP_SMC_STATUS_ERROR; 329 330 *retval = mmio_read_32(reg_addr); 331 332 return INTEL_SIP_SMC_STATUS_OK; 333 } 334 335 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 336 uint32_t *retval) 337 { 338 if (is_out_of_sec_range(reg_addr)) 339 return INTEL_SIP_SMC_STATUS_ERROR; 340 341 mmio_write_32(reg_addr, val); 342 343 return intel_secure_reg_read(reg_addr, retval); 344 } 345 346 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 347 uint32_t val, uint32_t *retval) 348 { 349 if (!intel_secure_reg_read(reg_addr, retval)) { 350 *retval &= ~mask; 351 *retval |= val & mask; 352 return intel_secure_reg_write(reg_addr, *retval, retval); 353 } 354 355 return INTEL_SIP_SMC_STATUS_ERROR; 356 } 357 358 /* Intel Remote System Update (RSU) services */ 359 uint64_t intel_rsu_update_address; 360 361 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 362 { 363 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 364 return INTEL_SIP_SMC_RSU_ERROR; 365 366 return INTEL_SIP_SMC_STATUS_OK; 367 } 368 369 static uint32_t intel_rsu_update(uint64_t update_address) 370 { 371 intel_rsu_update_address = update_address; 372 return INTEL_SIP_SMC_STATUS_OK; 373 } 374 375 static uint32_t intel_rsu_notify(uint32_t execution_stage) 376 { 377 if (mailbox_hps_stage_notify(execution_stage) < 0) 378 return INTEL_SIP_SMC_RSU_ERROR; 379 380 return INTEL_SIP_SMC_STATUS_OK; 381 } 382 383 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 384 uint32_t *ret_stat) 385 { 386 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 387 return INTEL_SIP_SMC_RSU_ERROR; 388 389 *ret_stat = respbuf[8]; 390 return INTEL_SIP_SMC_STATUS_OK; 391 } 392 393 /* Mailbox services */ 394 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 395 unsigned int len, 396 uint32_t urgent, uint32_t *response, 397 unsigned int resp_len, int *mbox_status, 398 unsigned int *len_in_resp) 399 { 400 *len_in_resp = 0; 401 *mbox_status = 0; 402 403 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) 404 return INTEL_SIP_SMC_STATUS_REJECTED; 405 406 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 407 response, &resp_len); 408 409 if (status < 0) { 410 *mbox_status = -status; 411 return INTEL_SIP_SMC_STATUS_ERROR; 412 } 413 414 *mbox_status = 0; 415 *len_in_resp = resp_len; 416 return INTEL_SIP_SMC_STATUS_OK; 417 } 418 419 /* 420 * This function is responsible for handling all SiP calls from the NS world 421 */ 422 423 uintptr_t sip_smc_handler(uint32_t smc_fid, 424 u_register_t x1, 425 u_register_t x2, 426 u_register_t x3, 427 u_register_t x4, 428 void *cookie, 429 void *handle, 430 u_register_t flags) 431 { 432 uint32_t retval = 0; 433 uint32_t status = INTEL_SIP_SMC_STATUS_OK; 434 uint32_t completed_addr[3]; 435 uint64_t rsu_respbuf[9]; 436 int mbox_status; 437 unsigned int len_in_resp; 438 u_register_t x5, x6; 439 440 switch (smc_fid) { 441 case SIP_SVC_UID: 442 /* Return UID to the caller */ 443 SMC_UUID_RET(handle, intl_svc_uid); 444 445 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 446 status = intel_mailbox_fpga_config_isdone(x1); 447 SMC_RET4(handle, status, 0, 0, 0); 448 449 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 450 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 451 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 452 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 453 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 454 455 case INTEL_SIP_SMC_FPGA_CONFIG_START: 456 status = intel_fpga_config_start(x1); 457 SMC_RET4(handle, status, 0, 0, 0); 458 459 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 460 status = intel_fpga_config_write(x1, x2); 461 SMC_RET4(handle, status, 0, 0, 0); 462 463 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 464 status = intel_fpga_config_completed_write(completed_addr, 465 &retval, &rcv_id); 466 switch (retval) { 467 case 1: 468 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 469 completed_addr[0], 0, 0); 470 471 case 2: 472 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 473 completed_addr[0], 474 completed_addr[1], 0); 475 476 case 3: 477 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 478 completed_addr[0], 479 completed_addr[1], 480 completed_addr[2]); 481 482 case 0: 483 SMC_RET4(handle, status, 0, 0, 0); 484 485 default: 486 mailbox_clear_response(); 487 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 488 } 489 490 case INTEL_SIP_SMC_REG_READ: 491 status = intel_secure_reg_read(x1, &retval); 492 SMC_RET3(handle, status, retval, x1); 493 494 case INTEL_SIP_SMC_REG_WRITE: 495 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 496 SMC_RET3(handle, status, retval, x1); 497 498 case INTEL_SIP_SMC_REG_UPDATE: 499 status = intel_secure_reg_update(x1, (uint32_t)x2, 500 (uint32_t)x3, &retval); 501 SMC_RET3(handle, status, retval, x1); 502 503 case INTEL_SIP_SMC_RSU_STATUS: 504 status = intel_rsu_status(rsu_respbuf, 505 ARRAY_SIZE(rsu_respbuf)); 506 if (status) { 507 SMC_RET1(handle, status); 508 } else { 509 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 510 rsu_respbuf[2], rsu_respbuf[3]); 511 } 512 513 case INTEL_SIP_SMC_RSU_UPDATE: 514 status = intel_rsu_update(x1); 515 SMC_RET1(handle, status); 516 517 case INTEL_SIP_SMC_RSU_NOTIFY: 518 status = intel_rsu_notify(x1); 519 SMC_RET1(handle, status); 520 521 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 522 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 523 ARRAY_SIZE(rsu_respbuf), &retval); 524 if (status) { 525 SMC_RET1(handle, status); 526 } else { 527 SMC_RET2(handle, status, retval); 528 } 529 530 case INTEL_SIP_SMC_MBOX_SEND_CMD: 531 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 532 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 533 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, 534 (uint32_t *)x5, x6, &mbox_status, 535 &len_in_resp); 536 SMC_RET3(handle, status, mbox_status, len_in_resp); 537 538 default: 539 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 540 cookie, handle, flags); 541 } 542 } 543 544 DECLARE_RT_SVC( 545 socfpga_sip_svc, 546 OEN_SIP_START, 547 OEN_SIP_END, 548 SMC_TYPE_FAST, 549 NULL, 550 sip_smc_handler 551 ); 552 553 DECLARE_RT_SVC( 554 socfpga_sip_svc_std, 555 OEN_SIP_START, 556 OEN_SIP_END, 557 SMC_TYPE_YIELD, 558 NULL, 559 sip_smc_handler 560 ); 561