1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_plat_def.h" 16 #include "socfpga_reset_manager.h" 17 #include "socfpga_sip_svc.h" 18 #include "socfpga_system_manager.h" 19 20 /* Total buffer the driver can hold */ 21 #define FPGA_CONFIG_BUFFER_SIZE 4 22 23 static config_type request_type = NO_REQUEST; 24 static int current_block, current_buffer; 25 static int read_block, max_blocks; 26 static uint32_t send_id, rcv_id; 27 static uint32_t bytes_per_block, blocks_submitted; 28 static bool bridge_disable; 29 30 /* RSU static variables */ 31 static uint32_t rsu_dcmf_ver[4] = {0}; 32 static uint16_t rsu_dcmf_stat[4] = {0}; 33 static uint32_t rsu_max_retry; 34 35 /* SiP Service UUID */ 36 DEFINE_SVC_UUID2(intl_svc_uid, 37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 39 40 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 41 uint64_t x1, 42 uint64_t x2, 43 uint64_t x3, 44 uint64_t x4, 45 void *cookie, 46 void *handle, 47 uint64_t flags) 48 { 49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 50 SMC_RET1(handle, SMC_UNK); 51 } 52 53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 54 55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 56 { 57 uint32_t args[3]; 58 59 while (max_blocks > 0 && buffer->size > buffer->size_written) { 60 args[0] = (1<<8); 61 args[1] = buffer->addr + buffer->size_written; 62 if (buffer->size - buffer->size_written <= bytes_per_block) { 63 args[2] = buffer->size - buffer->size_written; 64 current_buffer++; 65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 66 } else { 67 args[2] = bytes_per_block; 68 } 69 70 buffer->size_written += args[2]; 71 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 72 3U, CMD_INDIRECT); 73 74 buffer->subblocks_sent++; 75 max_blocks--; 76 } 77 78 return !max_blocks; 79 } 80 81 static int intel_fpga_sdm_write_all(void) 82 { 83 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 84 if (intel_fpga_sdm_write_buffer( 85 &fpga_config_buffers[current_buffer])) { 86 break; 87 } 88 } 89 return 0; 90 } 91 92 static uint32_t intel_mailbox_fpga_config_isdone(void) 93 { 94 uint32_t ret; 95 96 switch (request_type) { 97 case RECONFIGURATION: 98 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 99 true); 100 break; 101 case BITSTREAM_AUTH: 102 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 103 false); 104 break; 105 default: 106 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 107 false); 108 break; 109 } 110 111 if (ret != 0U) { 112 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 113 return INTEL_SIP_SMC_STATUS_BUSY; 114 } else { 115 request_type = NO_REQUEST; 116 return INTEL_SIP_SMC_STATUS_ERROR; 117 } 118 } 119 120 if (bridge_disable != 0U) { 121 socfpga_bridges_enable(~0); /* Enable bridge */ 122 bridge_disable = false; 123 } 124 request_type = NO_REQUEST; 125 126 return INTEL_SIP_SMC_STATUS_OK; 127 } 128 129 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 130 { 131 int i; 132 133 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 134 if (fpga_config_buffers[i].block_number == current_block) { 135 fpga_config_buffers[i].subblocks_sent--; 136 if (fpga_config_buffers[i].subblocks_sent == 0 137 && fpga_config_buffers[i].size <= 138 fpga_config_buffers[i].size_written) { 139 fpga_config_buffers[i].write_requested = 0; 140 current_block++; 141 *buffer_addr_completed = 142 fpga_config_buffers[i].addr; 143 return 0; 144 } 145 } 146 } 147 148 return -1; 149 } 150 151 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 152 uint32_t *count, uint32_t *job_id) 153 { 154 uint32_t resp[5]; 155 unsigned int resp_len = ARRAY_SIZE(resp); 156 int status = INTEL_SIP_SMC_STATUS_OK; 157 int all_completed = 1; 158 *count = 0; 159 160 while (*count < 3) { 161 162 status = mailbox_read_response(job_id, 163 resp, &resp_len); 164 165 if (status < 0) { 166 break; 167 } 168 169 max_blocks++; 170 171 if (mark_last_buffer_xfer_completed( 172 &completed_addr[*count]) == 0) { 173 *count = *count + 1; 174 } else { 175 break; 176 } 177 } 178 179 if (*count <= 0) { 180 if (status != MBOX_NO_RESPONSE && 181 status != MBOX_TIMEOUT && resp_len != 0) { 182 mailbox_clear_response(); 183 request_type = NO_REQUEST; 184 return INTEL_SIP_SMC_STATUS_ERROR; 185 } 186 187 *count = 0; 188 } 189 190 intel_fpga_sdm_write_all(); 191 192 if (*count > 0) { 193 status = INTEL_SIP_SMC_STATUS_OK; 194 } else if (*count == 0) { 195 status = INTEL_SIP_SMC_STATUS_BUSY; 196 } 197 198 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 199 if (fpga_config_buffers[i].write_requested != 0) { 200 all_completed = 0; 201 break; 202 } 203 } 204 205 if (all_completed == 1) { 206 return INTEL_SIP_SMC_STATUS_OK; 207 } 208 209 return status; 210 } 211 212 static int intel_fpga_config_start(uint32_t flag) 213 { 214 uint32_t argument = 0x1; 215 uint32_t response[3]; 216 int status = 0; 217 unsigned int size = 0; 218 unsigned int resp_len = ARRAY_SIZE(response); 219 220 request_type = RECONFIGURATION; 221 222 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 223 bridge_disable = true; 224 } 225 226 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 227 size = 1; 228 bridge_disable = false; 229 request_type = BITSTREAM_AUTH; 230 } 231 232 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 233 intel_smmu_hps_remapper_init(0U); 234 #endif 235 236 mailbox_clear_response(); 237 238 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 239 CMD_CASUAL, NULL, NULL); 240 241 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 242 CMD_CASUAL, response, &resp_len); 243 244 if (status < 0) { 245 bridge_disable = false; 246 request_type = NO_REQUEST; 247 return INTEL_SIP_SMC_STATUS_ERROR; 248 } 249 250 max_blocks = response[0]; 251 bytes_per_block = response[1]; 252 253 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 254 fpga_config_buffers[i].size = 0; 255 fpga_config_buffers[i].size_written = 0; 256 fpga_config_buffers[i].addr = 0; 257 fpga_config_buffers[i].write_requested = 0; 258 fpga_config_buffers[i].block_number = 0; 259 fpga_config_buffers[i].subblocks_sent = 0; 260 } 261 262 blocks_submitted = 0; 263 current_block = 0; 264 read_block = 0; 265 current_buffer = 0; 266 267 /* Disable bridge on full reconfiguration */ 268 if (bridge_disable) { 269 socfpga_bridges_disable(~0); 270 } 271 272 return INTEL_SIP_SMC_STATUS_OK; 273 } 274 275 static bool is_fpga_config_buffer_full(void) 276 { 277 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 278 if (!fpga_config_buffers[i].write_requested) { 279 return false; 280 } 281 } 282 return true; 283 } 284 285 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 286 { 287 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 288 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 289 290 if (!addr && !size) { 291 return true; 292 } 293 if (size > (UINT64_MAX - addr)) { 294 return false; 295 } 296 if (addr < BL31_LIMIT) { 297 return false; 298 } 299 if (dram_region_end > dram_max_sz) { 300 return false; 301 } 302 303 return true; 304 } 305 306 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 307 { 308 int i; 309 310 intel_fpga_sdm_write_all(); 311 312 if (!is_address_in_ddr_range(mem, size) || 313 is_fpga_config_buffer_full()) { 314 return INTEL_SIP_SMC_STATUS_REJECTED; 315 } 316 317 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 318 intel_smmu_hps_remapper_init(&mem); 319 #endif 320 321 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 322 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 323 324 if (!fpga_config_buffers[j].write_requested) { 325 fpga_config_buffers[j].addr = mem; 326 fpga_config_buffers[j].size = size; 327 fpga_config_buffers[j].size_written = 0; 328 fpga_config_buffers[j].write_requested = 1; 329 fpga_config_buffers[j].block_number = 330 blocks_submitted++; 331 fpga_config_buffers[j].subblocks_sent = 0; 332 break; 333 } 334 } 335 336 if (is_fpga_config_buffer_full()) { 337 return INTEL_SIP_SMC_STATUS_BUSY; 338 } 339 340 return INTEL_SIP_SMC_STATUS_OK; 341 } 342 343 static int is_out_of_sec_range(uint64_t reg_addr) 344 { 345 #if DEBUG 346 return 0; 347 #endif 348 349 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 350 switch (reg_addr) { 351 case(0xF8011100): /* ECCCTRL1 */ 352 case(0xF8011104): /* ECCCTRL2 */ 353 case(0xF8011110): /* ERRINTEN */ 354 case(0xF8011114): /* ERRINTENS */ 355 case(0xF8011118): /* ERRINTENR */ 356 case(0xF801111C): /* INTMODE */ 357 case(0xF8011120): /* INTSTAT */ 358 case(0xF8011124): /* DIAGINTTEST */ 359 case(0xF801112C): /* DERRADDRA */ 360 case(0xFA000000): /* SMMU SCR0 */ 361 case(0xFA000004): /* SMMU SCR1 */ 362 case(0xFA000400): /* SMMU NSCR0 */ 363 case(0xFA004000): /* SMMU SSD0_REG */ 364 case(0xFA000820): /* SMMU SMR8 */ 365 case(0xFA000c20): /* SMMU SCR8 */ 366 case(0xFA028000): /* SMMU CB8_SCTRL */ 367 case(0xFA001020): /* SMMU CBAR8 */ 368 case(0xFA028030): /* SMMU TCR_LPAE */ 369 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 370 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 371 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 372 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 373 case(0xFA028010): /* SMMU_CB8)TCR2 */ 374 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 375 case(0xFA001820): /* SMMU_CBA2R8 */ 376 case(0xFA000074): /* SMMU_STLBGSTATUS */ 377 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 378 case(0xFA000060): /* SMMU_STLBIALL */ 379 case(0xFA000070): /* SMMU_STLBGSYNC */ 380 case(0xFA028618): /* CB8_TLBALL */ 381 case(0xFA0287F0): /* CB8_TLBSYNC */ 382 case(0xFFD12028): /* SDMMCGRP_CTRL */ 383 case(0xFFD12044): /* EMAC0 */ 384 case(0xFFD12048): /* EMAC1 */ 385 case(0xFFD1204C): /* EMAC2 */ 386 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 387 case(0xFFD12094): /* ECC_INT_MASK_SET */ 388 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 389 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 390 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 391 case(0xFFD120C0): /* NOC_TIMEOUT */ 392 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 393 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 394 case(0xFFD120D0): /* NOC_IDLEACK */ 395 case(0xFFD120D4): /* NOC_IDLESTATUS */ 396 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 397 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 398 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 399 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 400 return 0; 401 #else 402 switch (reg_addr) { 403 404 case(0xF8011104): /* ECCCTRL2 */ 405 case(0xFFD12028): /* SDMMCGRP_CTRL */ 406 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 407 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 408 case(0xFFD120D0): /* NOC_IDLEACK */ 409 410 411 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 412 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 413 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 414 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 415 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 416 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 417 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 418 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 419 420 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 421 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 422 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 423 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 424 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 425 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 426 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 427 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 428 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 429 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 430 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 431 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 432 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 433 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 434 #endif 435 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 436 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 437 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 438 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 439 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 440 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 441 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 442 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 443 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 444 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 445 return 0; 446 447 default: 448 break; 449 } 450 451 return -1; 452 } 453 454 /* Secure register access */ 455 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 456 { 457 if (is_out_of_sec_range(reg_addr)) { 458 return INTEL_SIP_SMC_STATUS_ERROR; 459 } 460 461 *retval = mmio_read_32(reg_addr); 462 463 return INTEL_SIP_SMC_STATUS_OK; 464 } 465 466 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 467 uint32_t *retval) 468 { 469 if (is_out_of_sec_range(reg_addr)) { 470 return INTEL_SIP_SMC_STATUS_ERROR; 471 } 472 473 switch (reg_addr) { 474 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 475 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 476 mmio_write_16(reg_addr, val); 477 break; 478 default: 479 mmio_write_32(reg_addr, val); 480 break; 481 } 482 483 return intel_secure_reg_read(reg_addr, retval); 484 } 485 486 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 487 uint32_t val, uint32_t *retval) 488 { 489 if (!intel_secure_reg_read(reg_addr, retval)) { 490 *retval &= ~mask; 491 *retval |= val & mask; 492 return intel_secure_reg_write(reg_addr, *retval, retval); 493 } 494 495 return INTEL_SIP_SMC_STATUS_ERROR; 496 } 497 498 /* Intel Remote System Update (RSU) services */ 499 uint64_t intel_rsu_update_address; 500 501 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 502 { 503 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 504 return INTEL_SIP_SMC_RSU_ERROR; 505 } 506 507 return INTEL_SIP_SMC_STATUS_OK; 508 } 509 510 uint32_t intel_rsu_update(uint64_t update_address) 511 { 512 if (update_address > SIZE_MAX) { 513 return INTEL_SIP_SMC_STATUS_REJECTED; 514 } 515 516 intel_rsu_update_address = update_address; 517 return INTEL_SIP_SMC_STATUS_OK; 518 } 519 520 static uint32_t intel_rsu_notify(uint32_t execution_stage) 521 { 522 if (mailbox_hps_stage_notify(execution_stage) < 0) { 523 return INTEL_SIP_SMC_RSU_ERROR; 524 } 525 526 return INTEL_SIP_SMC_STATUS_OK; 527 } 528 529 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 530 uint32_t *ret_stat) 531 { 532 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 533 return INTEL_SIP_SMC_RSU_ERROR; 534 } 535 536 *ret_stat = respbuf[8]; 537 return INTEL_SIP_SMC_STATUS_OK; 538 } 539 540 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 541 uint64_t dcmf_ver_3_2) 542 { 543 rsu_dcmf_ver[0] = dcmf_ver_1_0; 544 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 545 rsu_dcmf_ver[2] = dcmf_ver_3_2; 546 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 547 548 return INTEL_SIP_SMC_STATUS_OK; 549 } 550 551 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 552 { 553 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 554 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 555 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 556 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 557 558 return INTEL_SIP_SMC_STATUS_OK; 559 } 560 561 /* Intel HWMON services */ 562 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 563 { 564 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 565 return INTEL_SIP_SMC_STATUS_ERROR; 566 } 567 568 return INTEL_SIP_SMC_STATUS_OK; 569 } 570 571 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 572 { 573 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 574 return INTEL_SIP_SMC_STATUS_ERROR; 575 } 576 577 return INTEL_SIP_SMC_STATUS_OK; 578 } 579 580 /* Mailbox services */ 581 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 582 { 583 int status; 584 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 585 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 586 587 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 588 CMD_CASUAL, resp_data, &resp_len); 589 590 if (status < 0) { 591 return INTEL_SIP_SMC_STATUS_ERROR; 592 } 593 594 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 595 return INTEL_SIP_SMC_STATUS_ERROR; 596 } 597 598 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 599 600 return INTEL_SIP_SMC_STATUS_OK; 601 } 602 603 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 604 unsigned int len, uint32_t urgent, uint64_t response, 605 unsigned int resp_len, int *mbox_status, 606 unsigned int *len_in_resp) 607 { 608 *len_in_resp = 0; 609 *mbox_status = GENERIC_RESPONSE_ERROR; 610 611 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 612 return INTEL_SIP_SMC_STATUS_REJECTED; 613 } 614 615 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 616 (uint32_t *) response, &resp_len); 617 618 if (status < 0) { 619 *mbox_status = -status; 620 return INTEL_SIP_SMC_STATUS_ERROR; 621 } 622 623 *mbox_status = 0; 624 *len_in_resp = resp_len; 625 626 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 627 628 return INTEL_SIP_SMC_STATUS_OK; 629 } 630 631 static int intel_smc_get_usercode(uint32_t *user_code) 632 { 633 int status; 634 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 635 636 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 637 0U, CMD_CASUAL, user_code, &resp_len); 638 639 if (status < 0) { 640 return INTEL_SIP_SMC_STATUS_ERROR; 641 } 642 643 return INTEL_SIP_SMC_STATUS_OK; 644 } 645 646 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 647 uint32_t mode, uint32_t *job_id, 648 uint32_t *ret_size, uint32_t *mbox_error) 649 { 650 int status = 0; 651 uint32_t resp_len = size / MBOX_WORD_BYTE; 652 653 if (resp_len > MBOX_DATA_MAX_LEN) { 654 return INTEL_SIP_SMC_STATUS_REJECTED; 655 } 656 657 if (!is_address_in_ddr_range(addr, size)) { 658 return INTEL_SIP_SMC_STATUS_REJECTED; 659 } 660 661 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 662 status = mailbox_read_response_async(job_id, 663 NULL, (uint32_t *) addr, &resp_len, 0); 664 } else { 665 status = mailbox_read_response(job_id, 666 (uint32_t *) addr, &resp_len); 667 668 if (status == MBOX_NO_RESPONSE) { 669 status = MBOX_BUSY; 670 } 671 } 672 673 if (status == MBOX_NO_RESPONSE) { 674 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 675 } 676 677 if (status == MBOX_BUSY) { 678 return INTEL_SIP_SMC_STATUS_BUSY; 679 } 680 681 *ret_size = resp_len * MBOX_WORD_BYTE; 682 flush_dcache_range(addr, *ret_size); 683 684 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 685 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 686 *mbox_error = -status; 687 } else if (status != MBOX_RET_OK) { 688 *mbox_error = -status; 689 return INTEL_SIP_SMC_STATUS_ERROR; 690 } 691 692 return INTEL_SIP_SMC_STATUS_OK; 693 } 694 695 /* Miscellaneous HPS services */ 696 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 697 { 698 int status = 0; 699 700 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 701 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 702 status = socfpga_bridges_enable((uint32_t)mask); 703 } else { 704 status = socfpga_bridges_enable(~0); 705 } 706 } else { 707 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 708 status = socfpga_bridges_disable((uint32_t)mask); 709 } else { 710 status = socfpga_bridges_disable(~0); 711 } 712 } 713 714 if (status < 0) { 715 return INTEL_SIP_SMC_STATUS_ERROR; 716 } 717 718 return INTEL_SIP_SMC_STATUS_OK; 719 } 720 721 /* SDM SEU Error services */ 722 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 723 { 724 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 725 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 726 } 727 728 return INTEL_SIP_SMC_STATUS_OK; 729 } 730 731 /* SDM SAFE SEU Error inject services */ 732 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 733 { 734 if (mailbox_safe_inject_seu_err(command, len) < 0) { 735 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 736 } 737 738 return INTEL_SIP_SMC_STATUS_OK; 739 } 740 741 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 742 /* SMMU HPS Remapper */ 743 void intel_smmu_hps_remapper_init(uint64_t *mem) 744 { 745 /* Read out Bit 1 value */ 746 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 747 748 if (remap == 0x00) { 749 /* Update DRAM Base address for SDM SMMU */ 750 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 751 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 752 *mem = *mem - DRAM_BASE; 753 } else { 754 *mem = *mem - DRAM_BASE; 755 } 756 } 757 #endif 758 759 /* 760 * This function is responsible for handling all SiP calls from the NS world 761 */ 762 763 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 764 u_register_t x1, 765 u_register_t x2, 766 u_register_t x3, 767 u_register_t x4, 768 void *cookie, 769 void *handle, 770 u_register_t flags) 771 { 772 uint32_t retval = 0, completed_addr[3]; 773 uint32_t retval2 = 0; 774 uint32_t mbox_error = 0; 775 uint64_t retval64, rsu_respbuf[9]; 776 uint32_t seu_respbuf[3]; 777 int status = INTEL_SIP_SMC_STATUS_OK; 778 int mbox_status; 779 unsigned int len_in_resp; 780 u_register_t x5, x6, x7; 781 782 switch (smc_fid) { 783 case SIP_SVC_UID: 784 /* Return UID to the caller */ 785 SMC_UUID_RET(handle, intl_svc_uid); 786 787 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 788 status = intel_mailbox_fpga_config_isdone(); 789 SMC_RET4(handle, status, 0, 0, 0); 790 791 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 792 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 793 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 794 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 795 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 796 797 case INTEL_SIP_SMC_FPGA_CONFIG_START: 798 status = intel_fpga_config_start(x1); 799 SMC_RET4(handle, status, 0, 0, 0); 800 801 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 802 status = intel_fpga_config_write(x1, x2); 803 SMC_RET4(handle, status, 0, 0, 0); 804 805 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 806 status = intel_fpga_config_completed_write(completed_addr, 807 &retval, &rcv_id); 808 switch (retval) { 809 case 1: 810 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 811 completed_addr[0], 0, 0); 812 813 case 2: 814 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 815 completed_addr[0], 816 completed_addr[1], 0); 817 818 case 3: 819 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 820 completed_addr[0], 821 completed_addr[1], 822 completed_addr[2]); 823 824 case 0: 825 SMC_RET4(handle, status, 0, 0, 0); 826 827 default: 828 mailbox_clear_response(); 829 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 830 } 831 832 case INTEL_SIP_SMC_REG_READ: 833 status = intel_secure_reg_read(x1, &retval); 834 SMC_RET3(handle, status, retval, x1); 835 836 case INTEL_SIP_SMC_REG_WRITE: 837 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 838 SMC_RET3(handle, status, retval, x1); 839 840 case INTEL_SIP_SMC_REG_UPDATE: 841 status = intel_secure_reg_update(x1, (uint32_t)x2, 842 (uint32_t)x3, &retval); 843 SMC_RET3(handle, status, retval, x1); 844 845 case INTEL_SIP_SMC_RSU_STATUS: 846 status = intel_rsu_status(rsu_respbuf, 847 ARRAY_SIZE(rsu_respbuf)); 848 if (status) { 849 SMC_RET1(handle, status); 850 } else { 851 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 852 rsu_respbuf[2], rsu_respbuf[3]); 853 } 854 855 case INTEL_SIP_SMC_RSU_UPDATE: 856 status = intel_rsu_update(x1); 857 SMC_RET1(handle, status); 858 859 case INTEL_SIP_SMC_RSU_NOTIFY: 860 status = intel_rsu_notify(x1); 861 SMC_RET1(handle, status); 862 863 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 864 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 865 ARRAY_SIZE(rsu_respbuf), &retval); 866 if (status) { 867 SMC_RET1(handle, status); 868 } else { 869 SMC_RET2(handle, status, retval); 870 } 871 872 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 873 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 874 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 875 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 876 877 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 878 status = intel_rsu_copy_dcmf_version(x1, x2); 879 SMC_RET1(handle, status); 880 881 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 882 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 883 ((uint64_t)rsu_dcmf_stat[3] << 48) | 884 ((uint64_t)rsu_dcmf_stat[2] << 32) | 885 ((uint64_t)rsu_dcmf_stat[1] << 16) | 886 rsu_dcmf_stat[0]); 887 888 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 889 status = intel_rsu_copy_dcmf_status(x1); 890 SMC_RET1(handle, status); 891 892 case INTEL_SIP_SMC_RSU_MAX_RETRY: 893 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 894 895 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 896 rsu_max_retry = x1; 897 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 898 899 case INTEL_SIP_SMC_ECC_DBE: 900 status = intel_ecc_dbe_notification(x1); 901 SMC_RET1(handle, status); 902 903 case INTEL_SIP_SMC_SERVICE_COMPLETED: 904 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 905 &len_in_resp, &mbox_error); 906 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 907 908 case INTEL_SIP_SMC_FIRMWARE_VERSION: 909 status = intel_smc_fw_version(&retval); 910 SMC_RET2(handle, status, retval); 911 912 case INTEL_SIP_SMC_MBOX_SEND_CMD: 913 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 914 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 915 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 916 &mbox_status, &len_in_resp); 917 SMC_RET3(handle, status, mbox_status, len_in_resp); 918 919 case INTEL_SIP_SMC_GET_USERCODE: 920 status = intel_smc_get_usercode(&retval); 921 SMC_RET2(handle, status, retval); 922 923 case INTEL_SIP_SMC_FCS_CRYPTION: 924 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 925 926 if (x1 == FCS_MODE_DECRYPT) { 927 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 928 } else if (x1 == FCS_MODE_ENCRYPT) { 929 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 930 } else { 931 status = INTEL_SIP_SMC_STATUS_REJECTED; 932 } 933 934 SMC_RET3(handle, status, x4, x5); 935 936 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 937 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 938 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 939 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 940 941 if (x3 == FCS_MODE_DECRYPT) { 942 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 943 (uint32_t *) &x7, &mbox_error); 944 } else if (x3 == FCS_MODE_ENCRYPT) { 945 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 946 (uint32_t *) &x7, &mbox_error); 947 } else { 948 status = INTEL_SIP_SMC_STATUS_REJECTED; 949 } 950 951 SMC_RET4(handle, status, mbox_error, x6, x7); 952 953 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 954 status = intel_fcs_random_number_gen(x1, &retval64, 955 &mbox_error); 956 SMC_RET4(handle, status, mbox_error, x1, retval64); 957 958 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 959 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 960 &send_id); 961 SMC_RET1(handle, status); 962 963 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 964 status = intel_fcs_send_cert(x1, x2, &send_id); 965 SMC_RET1(handle, status); 966 967 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 968 status = intel_fcs_get_provision_data(&send_id); 969 SMC_RET1(handle, status); 970 971 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 972 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 973 &mbox_error); 974 SMC_RET2(handle, status, mbox_error); 975 976 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 977 status = intel_hps_set_bridges(x1, x2); 978 SMC_RET1(handle, status); 979 980 case INTEL_SIP_SMC_HWMON_READTEMP: 981 status = intel_hwmon_readtemp(x1, &retval); 982 SMC_RET2(handle, status, retval); 983 984 case INTEL_SIP_SMC_HWMON_READVOLT: 985 status = intel_hwmon_readvolt(x1, &retval); 986 SMC_RET2(handle, status, retval); 987 988 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 989 status = intel_fcs_sigma_teardown(x1, &mbox_error); 990 SMC_RET2(handle, status, mbox_error); 991 992 case INTEL_SIP_SMC_FCS_CHIP_ID: 993 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 994 SMC_RET4(handle, status, mbox_error, retval, retval2); 995 996 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 997 status = intel_fcs_attestation_subkey(x1, x2, x3, 998 (uint32_t *) &x4, &mbox_error); 999 SMC_RET4(handle, status, mbox_error, x3, x4); 1000 1001 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 1002 status = intel_fcs_get_measurement(x1, x2, x3, 1003 (uint32_t *) &x4, &mbox_error); 1004 SMC_RET4(handle, status, mbox_error, x3, x4); 1005 1006 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 1007 status = intel_fcs_get_attestation_cert(x1, x2, 1008 (uint32_t *) &x3, &mbox_error); 1009 SMC_RET4(handle, status, mbox_error, x2, x3); 1010 1011 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 1012 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 1013 SMC_RET2(handle, status, mbox_error); 1014 1015 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 1016 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 1017 SMC_RET3(handle, status, mbox_error, retval); 1018 1019 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 1020 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 1021 SMC_RET2(handle, status, mbox_error); 1022 1023 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 1024 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 1025 SMC_RET1(handle, status); 1026 1027 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 1028 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 1029 (uint32_t *) &x4, &mbox_error); 1030 SMC_RET4(handle, status, mbox_error, x3, x4); 1031 1032 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 1033 status = intel_fcs_remove_crypto_service_key(x1, x2, 1034 &mbox_error); 1035 SMC_RET2(handle, status, mbox_error); 1036 1037 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 1038 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 1039 (uint32_t *) &x4, &mbox_error); 1040 SMC_RET4(handle, status, mbox_error, x3, x4); 1041 1042 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 1043 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1044 status = intel_fcs_get_digest_init(x1, x2, x3, 1045 x4, x5, &mbox_error); 1046 SMC_RET2(handle, status, mbox_error); 1047 1048 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 1049 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1050 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1051 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1052 x4, x5, (uint32_t *) &x6, false, 1053 &mbox_error); 1054 SMC_RET4(handle, status, mbox_error, x5, x6); 1055 1056 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 1057 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1058 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1059 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1060 x4, x5, (uint32_t *) &x6, true, 1061 &mbox_error); 1062 SMC_RET4(handle, status, mbox_error, x5, x6); 1063 1064 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 1065 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1066 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1067 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1068 x4, x5, (uint32_t *) &x6, false, 1069 &mbox_error, &send_id); 1070 SMC_RET4(handle, status, mbox_error, x5, x6); 1071 1072 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 1073 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1074 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1075 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1076 x4, x5, (uint32_t *) &x6, true, 1077 &mbox_error, &send_id); 1078 SMC_RET4(handle, status, mbox_error, x5, x6); 1079 1080 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 1081 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1082 status = intel_fcs_mac_verify_init(x1, x2, x3, 1083 x4, x5, &mbox_error); 1084 SMC_RET2(handle, status, mbox_error); 1085 1086 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 1087 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1088 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1089 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1090 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1091 x4, x5, (uint32_t *) &x6, x7, 1092 false, &mbox_error); 1093 SMC_RET4(handle, status, mbox_error, x5, x6); 1094 1095 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 1096 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1097 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1098 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1099 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1100 x4, x5, (uint32_t *) &x6, x7, 1101 true, &mbox_error); 1102 SMC_RET4(handle, status, mbox_error, x5, x6); 1103 1104 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 1105 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1106 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1107 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1108 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1109 x4, x5, (uint32_t *) &x6, x7, 1110 false, &mbox_error, &send_id); 1111 SMC_RET4(handle, status, mbox_error, x5, x6); 1112 1113 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 1114 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1115 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1116 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1117 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1118 x4, x5, (uint32_t *) &x6, x7, 1119 true, &mbox_error, &send_id); 1120 SMC_RET4(handle, status, mbox_error, x5, x6); 1121 1122 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1123 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1124 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 1125 x4, x5, &mbox_error); 1126 SMC_RET2(handle, status, mbox_error); 1127 1128 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1129 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1130 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1131 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1132 x3, x4, x5, (uint32_t *) &x6, false, 1133 &mbox_error); 1134 SMC_RET4(handle, status, mbox_error, x5, x6); 1135 1136 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1137 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1138 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1139 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1140 x3, x4, x5, (uint32_t *) &x6, true, 1141 &mbox_error); 1142 SMC_RET4(handle, status, mbox_error, x5, x6); 1143 1144 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1145 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1146 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1147 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1148 x2, x3, x4, x5, (uint32_t *) &x6, false, 1149 &mbox_error, &send_id); 1150 SMC_RET4(handle, status, mbox_error, x5, x6); 1151 1152 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1153 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1154 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1155 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1156 x2, x3, x4, x5, (uint32_t *) &x6, true, 1157 &mbox_error, &send_id); 1158 SMC_RET4(handle, status, mbox_error, x5, x6); 1159 1160 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 1161 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1162 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 1163 x4, x5, &mbox_error); 1164 SMC_RET2(handle, status, mbox_error); 1165 1166 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1167 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1168 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1169 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 1170 x4, x5, (uint32_t *) &x6, &mbox_error); 1171 SMC_RET4(handle, status, mbox_error, x5, x6); 1172 1173 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1174 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1175 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 1176 x4, x5, &mbox_error); 1177 SMC_RET2(handle, status, mbox_error); 1178 1179 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1180 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1181 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1182 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 1183 x4, x5, (uint32_t *) &x6, &mbox_error); 1184 SMC_RET4(handle, status, mbox_error, x5, x6); 1185 1186 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1187 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1188 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 1189 x4, x5, &mbox_error); 1190 SMC_RET2(handle, status, mbox_error); 1191 1192 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1193 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1194 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1195 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1196 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1197 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1198 x7, false, &mbox_error); 1199 SMC_RET4(handle, status, mbox_error, x5, x6); 1200 1201 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1202 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1203 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1204 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1205 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1206 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1207 x7, false, &mbox_error, &send_id); 1208 SMC_RET4(handle, status, mbox_error, x5, x6); 1209 1210 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1211 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1212 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1213 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1214 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1215 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1216 x7, true, &mbox_error, &send_id); 1217 SMC_RET4(handle, status, mbox_error, x5, x6); 1218 1219 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1220 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1221 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1222 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1223 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1224 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1225 x7, true, &mbox_error); 1226 SMC_RET4(handle, status, mbox_error, x5, x6); 1227 1228 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1229 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1230 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1231 x4, x5, &mbox_error); 1232 SMC_RET2(handle, status, mbox_error); 1233 1234 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1235 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1236 (uint32_t *) &x4, &mbox_error); 1237 SMC_RET4(handle, status, mbox_error, x3, x4); 1238 1239 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1240 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1241 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1242 x4, x5, &mbox_error); 1243 SMC_RET2(handle, status, mbox_error); 1244 1245 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1246 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1247 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1248 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1249 x4, x5, (uint32_t *) &x6, &mbox_error); 1250 SMC_RET4(handle, status, mbox_error, x5, x6); 1251 1252 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1253 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1254 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1255 &mbox_error); 1256 SMC_RET2(handle, status, mbox_error); 1257 1258 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1259 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1260 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1261 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1262 x5, x6, false, &send_id); 1263 SMC_RET1(handle, status); 1264 1265 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1266 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1267 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1268 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1269 x5, x6, true, &send_id); 1270 SMC_RET1(handle, status); 1271 1272 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1273 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1274 &mbox_error); 1275 SMC_RET4(handle, status, mbox_error, x1, retval64); 1276 1277 case INTEL_SIP_SMC_SVC_VERSION: 1278 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1279 SIP_SVC_VERSION_MAJOR, 1280 SIP_SVC_VERSION_MINOR); 1281 1282 case INTEL_SIP_SMC_SEU_ERR_STATUS: 1283 status = intel_sdm_seu_err_read(seu_respbuf, 1284 ARRAY_SIZE(seu_respbuf)); 1285 if (status) { 1286 SMC_RET1(handle, status); 1287 } else { 1288 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 1289 } 1290 1291 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 1292 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 1293 SMC_RET1(handle, status); 1294 1295 default: 1296 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1297 cookie, handle, flags); 1298 } 1299 } 1300 1301 uintptr_t sip_smc_handler(uint32_t smc_fid, 1302 u_register_t x1, 1303 u_register_t x2, 1304 u_register_t x3, 1305 u_register_t x4, 1306 void *cookie, 1307 void *handle, 1308 u_register_t flags) 1309 { 1310 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1311 1312 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1313 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1314 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1315 cookie, handle, flags); 1316 } else { 1317 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1318 cookie, handle, flags); 1319 } 1320 } 1321 1322 DECLARE_RT_SVC( 1323 socfpga_sip_svc, 1324 OEN_SIP_START, 1325 OEN_SIP_END, 1326 SMC_TYPE_FAST, 1327 NULL, 1328 sip_smc_handler 1329 ); 1330 1331 DECLARE_RT_SVC( 1332 socfpga_sip_svc_std, 1333 OEN_SIP_START, 1334 OEN_SIP_END, 1335 SMC_TYPE_YIELD, 1336 NULL, 1337 sip_smc_handler 1338 ); 1339