1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <common/debug.h> 11 #include <common/runtime_svc.h> 12 #include <lib/mmio.h> 13 #include <tools_share/uuid.h> 14 15 #include "socfpga_fcs.h" 16 #include "socfpga_mailbox.h" 17 #include "socfpga_plat_def.h" 18 #include "socfpga_reset_manager.h" 19 #include "socfpga_sip_svc.h" 20 #include "socfpga_system_manager.h" 21 22 /* Total buffer the driver can hold */ 23 #define FPGA_CONFIG_BUFFER_SIZE 4 24 25 static config_type request_type = NO_REQUEST; 26 static int current_block, current_buffer; 27 static int read_block, max_blocks; 28 static uint32_t send_id, rcv_id; 29 static uint32_t bytes_per_block, blocks_submitted; 30 static bool bridge_disable; 31 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 32 static uint32_t g_remapper_bypass; 33 #endif 34 35 /* RSU static variables */ 36 static uint32_t rsu_dcmf_ver[4] = {0}; 37 static uint16_t rsu_dcmf_stat[4] = {0}; 38 static uint32_t rsu_max_retry; 39 40 /* SiP Service UUID */ 41 DEFINE_SVC_UUID2(intl_svc_uid, 42 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 43 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 44 45 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 46 uint64_t x1, 47 uint64_t x2, 48 uint64_t x3, 49 uint64_t x4, 50 void *cookie, 51 void *handle, 52 uint64_t flags) 53 { 54 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 55 SMC_RET1(handle, SMC_UNK); 56 } 57 58 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 59 60 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 61 { 62 uint32_t args[3]; 63 64 while (max_blocks > 0 && buffer->size > buffer->size_written) { 65 args[0] = (1<<8); 66 args[1] = buffer->addr + buffer->size_written; 67 if (buffer->size - buffer->size_written <= bytes_per_block) { 68 args[2] = buffer->size - buffer->size_written; 69 current_buffer++; 70 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 71 } else { 72 args[2] = bytes_per_block; 73 } 74 75 buffer->size_written += args[2]; 76 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 77 3U, CMD_INDIRECT); 78 79 buffer->subblocks_sent++; 80 max_blocks--; 81 } 82 83 return !max_blocks; 84 } 85 86 static int intel_fpga_sdm_write_all(void) 87 { 88 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 89 if (intel_fpga_sdm_write_buffer( 90 &fpga_config_buffers[current_buffer])) { 91 break; 92 } 93 } 94 return 0; 95 } 96 97 static uint32_t intel_mailbox_fpga_config_isdone(void) 98 { 99 uint32_t ret; 100 101 switch (request_type) { 102 case RECONFIGURATION: 103 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 104 true); 105 break; 106 case BITSTREAM_AUTH: 107 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 108 false); 109 break; 110 default: 111 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 112 false); 113 break; 114 } 115 116 if (ret != 0U) { 117 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 118 return INTEL_SIP_SMC_STATUS_BUSY; 119 } else { 120 request_type = NO_REQUEST; 121 return INTEL_SIP_SMC_STATUS_ERROR; 122 } 123 } 124 125 if (bridge_disable != 0U) { 126 socfpga_bridges_enable(~0); /* Enable bridge */ 127 bridge_disable = false; 128 } 129 request_type = NO_REQUEST; 130 131 return INTEL_SIP_SMC_STATUS_OK; 132 } 133 134 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 135 { 136 int i; 137 138 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 139 if (fpga_config_buffers[i].block_number == current_block) { 140 fpga_config_buffers[i].subblocks_sent--; 141 if (fpga_config_buffers[i].subblocks_sent == 0 142 && fpga_config_buffers[i].size <= 143 fpga_config_buffers[i].size_written) { 144 fpga_config_buffers[i].write_requested = 0; 145 current_block++; 146 *buffer_addr_completed = 147 fpga_config_buffers[i].addr; 148 return 0; 149 } 150 } 151 } 152 153 return -1; 154 } 155 156 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 157 uint32_t *count, uint32_t *job_id) 158 { 159 uint32_t resp[5]; 160 unsigned int resp_len = ARRAY_SIZE(resp); 161 int status = INTEL_SIP_SMC_STATUS_OK; 162 int all_completed = 1; 163 *count = 0; 164 165 while (*count < 3) { 166 167 status = mailbox_read_response(job_id, 168 resp, &resp_len); 169 170 if (status < 0) { 171 break; 172 } 173 174 max_blocks++; 175 176 if (mark_last_buffer_xfer_completed( 177 &completed_addr[*count]) == 0) { 178 *count = *count + 1; 179 } else { 180 break; 181 } 182 } 183 184 if (*count <= 0) { 185 if (status != MBOX_NO_RESPONSE && 186 status != MBOX_TIMEOUT && resp_len != 0) { 187 mailbox_clear_response(); 188 request_type = NO_REQUEST; 189 return INTEL_SIP_SMC_STATUS_ERROR; 190 } 191 192 *count = 0; 193 } 194 195 intel_fpga_sdm_write_all(); 196 197 if (*count > 0) { 198 status = INTEL_SIP_SMC_STATUS_OK; 199 } else if (*count == 0) { 200 status = INTEL_SIP_SMC_STATUS_BUSY; 201 } 202 203 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 204 if (fpga_config_buffers[i].write_requested != 0) { 205 all_completed = 0; 206 break; 207 } 208 } 209 210 if (all_completed == 1) { 211 return INTEL_SIP_SMC_STATUS_OK; 212 } 213 214 return status; 215 } 216 217 static int intel_fpga_config_start(uint32_t flag) 218 { 219 uint32_t argument = 0x1; 220 uint32_t response[3]; 221 int status = 0; 222 unsigned int size = 0; 223 unsigned int resp_len = ARRAY_SIZE(response); 224 225 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 226 /* 227 * To trigger isolation 228 * FPGA configuration complete signal should be de-asserted 229 */ 230 INFO("SOCFPGA: Request SDM to trigger isolation\n"); 231 status = mailbox_send_fpga_config_comp(); 232 233 if (status < 0) { 234 INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n"); 235 } 236 #endif 237 238 request_type = RECONFIGURATION; 239 240 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 241 bridge_disable = true; 242 } 243 244 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 245 size = 1; 246 bridge_disable = false; 247 request_type = BITSTREAM_AUTH; 248 } 249 250 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 251 intel_smmu_hps_remapper_init(0U); 252 #endif 253 254 mailbox_clear_response(); 255 256 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 257 CMD_CASUAL, NULL, NULL); 258 259 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 260 CMD_CASUAL, response, &resp_len); 261 262 if (status < 0) { 263 bridge_disable = false; 264 request_type = NO_REQUEST; 265 return INTEL_SIP_SMC_STATUS_ERROR; 266 } 267 268 max_blocks = response[0]; 269 bytes_per_block = response[1]; 270 271 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 272 fpga_config_buffers[i].size = 0; 273 fpga_config_buffers[i].size_written = 0; 274 fpga_config_buffers[i].addr = 0; 275 fpga_config_buffers[i].write_requested = 0; 276 fpga_config_buffers[i].block_number = 0; 277 fpga_config_buffers[i].subblocks_sent = 0; 278 } 279 280 blocks_submitted = 0; 281 current_block = 0; 282 read_block = 0; 283 current_buffer = 0; 284 285 /* Disable bridge on full reconfiguration */ 286 if (bridge_disable) { 287 socfpga_bridges_disable(~0); 288 } 289 290 return INTEL_SIP_SMC_STATUS_OK; 291 } 292 293 static bool is_fpga_config_buffer_full(void) 294 { 295 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 296 if (!fpga_config_buffers[i].write_requested) { 297 return false; 298 } 299 } 300 return true; 301 } 302 303 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 304 { 305 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 306 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 307 308 if (!addr && !size) { 309 return true; 310 } 311 if (size > (UINT64_MAX - addr)) { 312 return false; 313 } 314 if (addr < BL31_LIMIT) { 315 return false; 316 } 317 if (dram_region_end > dram_max_sz) { 318 return false; 319 } 320 321 return true; 322 } 323 324 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 325 { 326 int i; 327 328 intel_fpga_sdm_write_all(); 329 330 if (!is_address_in_ddr_range(mem, size) || 331 is_fpga_config_buffer_full()) { 332 return INTEL_SIP_SMC_STATUS_REJECTED; 333 } 334 335 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 336 intel_smmu_hps_remapper_init(&mem); 337 #endif 338 339 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 340 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 341 342 if (!fpga_config_buffers[j].write_requested) { 343 fpga_config_buffers[j].addr = mem; 344 fpga_config_buffers[j].size = size; 345 fpga_config_buffers[j].size_written = 0; 346 fpga_config_buffers[j].write_requested = 1; 347 fpga_config_buffers[j].block_number = 348 blocks_submitted++; 349 fpga_config_buffers[j].subblocks_sent = 0; 350 break; 351 } 352 } 353 354 if (is_fpga_config_buffer_full()) { 355 return INTEL_SIP_SMC_STATUS_BUSY; 356 } 357 358 return INTEL_SIP_SMC_STATUS_OK; 359 } 360 361 static int is_out_of_sec_range(uint64_t reg_addr) 362 { 363 #if DEBUG 364 return 0; 365 #endif 366 367 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 368 switch (reg_addr) { 369 case(0xF8011100): /* ECCCTRL1 */ 370 case(0xF8011104): /* ECCCTRL2 */ 371 case(0xF8011110): /* ERRINTEN */ 372 case(0xF8011114): /* ERRINTENS */ 373 case(0xF8011118): /* ERRINTENR */ 374 case(0xF801111C): /* INTMODE */ 375 case(0xF8011120): /* INTSTAT */ 376 case(0xF8011124): /* DIAGINTTEST */ 377 case(0xF801112C): /* DERRADDRA */ 378 case(0xFA000000): /* SMMU SCR0 */ 379 case(0xFA000004): /* SMMU SCR1 */ 380 case(0xFA000400): /* SMMU NSCR0 */ 381 case(0xFA004000): /* SMMU SSD0_REG */ 382 case(0xFA000820): /* SMMU SMR8 */ 383 case(0xFA000c20): /* SMMU SCR8 */ 384 case(0xFA028000): /* SMMU CB8_SCTRL */ 385 case(0xFA001020): /* SMMU CBAR8 */ 386 case(0xFA028030): /* SMMU TCR_LPAE */ 387 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 388 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 389 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 390 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 391 case(0xFA028010): /* SMMU_CB8)TCR2 */ 392 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 393 case(0xFA001820): /* SMMU_CBA2R8 */ 394 case(0xFA000074): /* SMMU_STLBGSTATUS */ 395 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 396 case(0xFA000060): /* SMMU_STLBIALL */ 397 case(0xFA000070): /* SMMU_STLBGSYNC */ 398 case(0xFA028618): /* CB8_TLBALL */ 399 case(0xFA0287F0): /* CB8_TLBSYNC */ 400 case(0xFFD12028): /* SDMMCGRP_CTRL */ 401 case(0xFFD12044): /* EMAC0 */ 402 case(0xFFD12048): /* EMAC1 */ 403 case(0xFFD1204C): /* EMAC2 */ 404 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 405 case(0xFFD12094): /* ECC_INT_MASK_SET */ 406 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 407 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 408 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 409 case(0xFFD120C0): /* NOC_TIMEOUT */ 410 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 411 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 412 case(0xFFD120D0): /* NOC_IDLEACK */ 413 case(0xFFD120D4): /* NOC_IDLESTATUS */ 414 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 415 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 416 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 417 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 418 return 0; 419 #else 420 switch (reg_addr) { 421 422 case(0xF8011104): /* ECCCTRL2 */ 423 case(0xFFD12028): /* SDMMCGRP_CTRL */ 424 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 425 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 426 case(0xFFD120D0): /* NOC_IDLEACK */ 427 428 429 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 430 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 431 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 432 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 433 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 434 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 435 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 436 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 437 438 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */ 439 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 440 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 441 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 442 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 443 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 444 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 445 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 446 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 447 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 448 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 449 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 450 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 451 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 452 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 453 #endif 454 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 455 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 456 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 457 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 458 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 459 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 460 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 461 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 462 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 463 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 464 return 0; 465 466 default: 467 break; 468 } 469 470 return -1; 471 } 472 473 /* Secure register access */ 474 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 475 { 476 if (is_out_of_sec_range(reg_addr)) { 477 return INTEL_SIP_SMC_STATUS_ERROR; 478 } 479 480 *retval = mmio_read_32(reg_addr); 481 482 return INTEL_SIP_SMC_STATUS_OK; 483 } 484 485 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 486 uint32_t *retval) 487 { 488 if (is_out_of_sec_range(reg_addr)) { 489 return INTEL_SIP_SMC_STATUS_ERROR; 490 } 491 492 switch (reg_addr) { 493 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 494 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 495 mmio_write_16(reg_addr, val); 496 break; 497 default: 498 mmio_write_32(reg_addr, val); 499 break; 500 } 501 502 return intel_secure_reg_read(reg_addr, retval); 503 } 504 505 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 506 uint32_t val, uint32_t *retval) 507 { 508 if (!intel_secure_reg_read(reg_addr, retval)) { 509 *retval &= ~mask; 510 *retval |= val & mask; 511 return intel_secure_reg_write(reg_addr, *retval, retval); 512 } 513 514 return INTEL_SIP_SMC_STATUS_ERROR; 515 } 516 517 /* Intel Remote System Update (RSU) services */ 518 uint64_t intel_rsu_update_address; 519 520 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 521 { 522 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 523 return INTEL_SIP_SMC_RSU_ERROR; 524 } 525 526 return INTEL_SIP_SMC_STATUS_OK; 527 } 528 529 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf, 530 unsigned int respbuf_sz) 531 { 532 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) { 533 return INTEL_SIP_SMC_RSU_ERROR; 534 } 535 536 return INTEL_SIP_SMC_STATUS_OK; 537 } 538 539 uint32_t intel_rsu_update(uint64_t update_address) 540 { 541 if (update_address > SIZE_MAX) { 542 return INTEL_SIP_SMC_STATUS_REJECTED; 543 } 544 545 intel_rsu_update_address = update_address; 546 return INTEL_SIP_SMC_STATUS_OK; 547 } 548 549 static uint32_t intel_rsu_notify(uint32_t execution_stage) 550 { 551 if (mailbox_hps_stage_notify(execution_stage) < 0) { 552 return INTEL_SIP_SMC_RSU_ERROR; 553 } 554 555 return INTEL_SIP_SMC_STATUS_OK; 556 } 557 558 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 559 uint32_t *ret_stat) 560 { 561 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 562 return INTEL_SIP_SMC_RSU_ERROR; 563 } 564 565 *ret_stat = respbuf[8]; 566 return INTEL_SIP_SMC_STATUS_OK; 567 } 568 569 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 570 uint64_t dcmf_ver_3_2) 571 { 572 rsu_dcmf_ver[0] = dcmf_ver_1_0; 573 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 574 rsu_dcmf_ver[2] = dcmf_ver_3_2; 575 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 576 577 return INTEL_SIP_SMC_STATUS_OK; 578 } 579 580 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 581 { 582 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 583 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 584 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 585 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 586 587 return INTEL_SIP_SMC_STATUS_OK; 588 } 589 590 /* Intel HWMON services */ 591 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 592 { 593 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 594 return INTEL_SIP_SMC_STATUS_ERROR; 595 } 596 597 return INTEL_SIP_SMC_STATUS_OK; 598 } 599 600 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 601 { 602 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 603 return INTEL_SIP_SMC_STATUS_ERROR; 604 } 605 606 return INTEL_SIP_SMC_STATUS_OK; 607 } 608 609 /* Mailbox services */ 610 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 611 { 612 int status; 613 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 614 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 615 616 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 617 CMD_CASUAL, resp_data, &resp_len); 618 619 if (status < 0) { 620 return INTEL_SIP_SMC_STATUS_ERROR; 621 } 622 623 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 624 return INTEL_SIP_SMC_STATUS_ERROR; 625 } 626 627 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 628 629 return INTEL_SIP_SMC_STATUS_OK; 630 } 631 632 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 633 unsigned int len, uint32_t urgent, uint64_t response, 634 unsigned int resp_len, int *mbox_status, 635 unsigned int *len_in_resp) 636 { 637 *len_in_resp = 0; 638 *mbox_status = GENERIC_RESPONSE_ERROR; 639 640 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 641 return INTEL_SIP_SMC_STATUS_REJECTED; 642 } 643 644 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 645 (uint32_t *) response, &resp_len); 646 647 if (status < 0) { 648 *mbox_status = -status; 649 return INTEL_SIP_SMC_STATUS_ERROR; 650 } 651 652 *mbox_status = 0; 653 *len_in_resp = resp_len; 654 655 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 656 657 return INTEL_SIP_SMC_STATUS_OK; 658 } 659 660 static int intel_smc_get_usercode(uint32_t *user_code) 661 { 662 int status; 663 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 664 665 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 666 0U, CMD_CASUAL, user_code, &resp_len); 667 668 if (status < 0) { 669 return INTEL_SIP_SMC_STATUS_ERROR; 670 } 671 672 return INTEL_SIP_SMC_STATUS_OK; 673 } 674 675 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 676 uint32_t mode, uint32_t *job_id, 677 uint32_t *ret_size, uint32_t *mbox_error) 678 { 679 int status = 0; 680 uint32_t resp_len = size / MBOX_WORD_BYTE; 681 682 if (resp_len > MBOX_DATA_MAX_LEN) { 683 return INTEL_SIP_SMC_STATUS_REJECTED; 684 } 685 686 if (!is_address_in_ddr_range(addr, size)) { 687 return INTEL_SIP_SMC_STATUS_REJECTED; 688 } 689 690 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 691 status = mailbox_read_response_async(job_id, 692 NULL, (uint32_t *) addr, &resp_len, 0); 693 } else { 694 status = mailbox_read_response(job_id, 695 (uint32_t *) addr, &resp_len); 696 697 if (status == MBOX_NO_RESPONSE) { 698 status = MBOX_BUSY; 699 } 700 } 701 702 if (status == MBOX_NO_RESPONSE) { 703 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 704 } 705 706 if (status == MBOX_BUSY) { 707 return INTEL_SIP_SMC_STATUS_BUSY; 708 } 709 710 *ret_size = resp_len * MBOX_WORD_BYTE; 711 flush_dcache_range(addr, *ret_size); 712 713 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 714 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 715 *mbox_error = -status; 716 } else if (status != MBOX_RET_OK) { 717 *mbox_error = -status; 718 return INTEL_SIP_SMC_STATUS_ERROR; 719 } 720 721 return INTEL_SIP_SMC_STATUS_OK; 722 } 723 724 /* Miscellaneous HPS services */ 725 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 726 { 727 int status = 0; 728 729 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 730 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 731 status = socfpga_bridges_enable((uint32_t)mask); 732 } else { 733 status = socfpga_bridges_enable(~0); 734 } 735 } else { 736 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 737 status = socfpga_bridges_disable((uint32_t)mask); 738 } else { 739 status = socfpga_bridges_disable(~0); 740 } 741 } 742 743 if (status < 0) { 744 return INTEL_SIP_SMC_STATUS_ERROR; 745 } 746 747 return INTEL_SIP_SMC_STATUS_OK; 748 } 749 750 /* SDM SEU Error services */ 751 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 752 { 753 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 754 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 755 } 756 757 return INTEL_SIP_SMC_STATUS_OK; 758 } 759 760 /* SDM SAFE SEU Error inject services */ 761 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 762 { 763 if (mailbox_safe_inject_seu_err(command, len) < 0) { 764 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 765 } 766 767 return INTEL_SIP_SMC_STATUS_OK; 768 } 769 770 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 771 /* SMMU HPS Remapper */ 772 void intel_smmu_hps_remapper_init(uint64_t *mem) 773 { 774 /* Read out Bit 1 value */ 775 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 776 777 if ((remap == 0x00) && (g_remapper_bypass == 0x00)) { 778 /* Update DRAM Base address for SDM SMMU */ 779 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 780 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 781 *mem = *mem - DRAM_BASE; 782 } else { 783 *mem = *mem - DRAM_BASE; 784 } 785 } 786 787 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass) 788 { 789 /* Read out the JTAG-ID from boot scratch register */ 790 if (is_agilex5_A5F0() != 0) { 791 if (remapper_bypass == 0x01) { 792 g_remapper_bypass = remapper_bypass; 793 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0); 794 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0); 795 } 796 } 797 return INTEL_SIP_SMC_STATUS_OK; 798 } 799 #endif 800 801 /* 802 * This function is responsible for handling all SiP calls from the NS world 803 */ 804 805 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 806 u_register_t x1, 807 u_register_t x2, 808 u_register_t x3, 809 u_register_t x4, 810 void *cookie, 811 void *handle, 812 u_register_t flags) 813 { 814 uint32_t retval = 0, completed_addr[3]; 815 uint32_t retval2 = 0; 816 uint32_t mbox_error = 0; 817 uint64_t retval64, rsu_respbuf[9]; 818 uint32_t seu_respbuf[3]; 819 int status = INTEL_SIP_SMC_STATUS_OK; 820 int mbox_status; 821 unsigned int len_in_resp; 822 u_register_t x5, x6, x7; 823 824 switch (smc_fid) { 825 case SIP_SVC_UID: 826 /* Return UID to the caller */ 827 SMC_UUID_RET(handle, intl_svc_uid); 828 829 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 830 status = intel_mailbox_fpga_config_isdone(); 831 SMC_RET4(handle, status, 0, 0, 0); 832 833 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 834 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 835 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 836 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 837 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 838 839 case INTEL_SIP_SMC_FPGA_CONFIG_START: 840 status = intel_fpga_config_start(x1); 841 SMC_RET4(handle, status, 0, 0, 0); 842 843 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 844 status = intel_fpga_config_write(x1, x2); 845 SMC_RET4(handle, status, 0, 0, 0); 846 847 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 848 status = intel_fpga_config_completed_write(completed_addr, 849 &retval, &rcv_id); 850 switch (retval) { 851 case 1: 852 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 853 completed_addr[0], 0, 0); 854 855 case 2: 856 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 857 completed_addr[0], 858 completed_addr[1], 0); 859 860 case 3: 861 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 862 completed_addr[0], 863 completed_addr[1], 864 completed_addr[2]); 865 866 case 0: 867 SMC_RET4(handle, status, 0, 0, 0); 868 869 default: 870 mailbox_clear_response(); 871 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 872 } 873 874 case INTEL_SIP_SMC_REG_READ: 875 status = intel_secure_reg_read(x1, &retval); 876 SMC_RET3(handle, status, retval, x1); 877 878 case INTEL_SIP_SMC_REG_WRITE: 879 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 880 SMC_RET3(handle, status, retval, x1); 881 882 case INTEL_SIP_SMC_REG_UPDATE: 883 status = intel_secure_reg_update(x1, (uint32_t)x2, 884 (uint32_t)x3, &retval); 885 SMC_RET3(handle, status, retval, x1); 886 887 case INTEL_SIP_SMC_RSU_STATUS: 888 status = intel_rsu_status(rsu_respbuf, 889 ARRAY_SIZE(rsu_respbuf)); 890 if (status) { 891 SMC_RET1(handle, status); 892 } else { 893 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 894 rsu_respbuf[2], rsu_respbuf[3]); 895 } 896 897 case INTEL_SIP_SMC_RSU_UPDATE: 898 status = intel_rsu_update(x1); 899 SMC_RET1(handle, status); 900 901 case INTEL_SIP_SMC_RSU_NOTIFY: 902 status = intel_rsu_notify(x1); 903 SMC_RET1(handle, status); 904 905 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 906 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 907 ARRAY_SIZE(rsu_respbuf), &retval); 908 if (status) { 909 SMC_RET1(handle, status); 910 } else { 911 SMC_RET2(handle, status, retval); 912 } 913 914 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 915 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 916 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 917 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 918 919 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 920 status = intel_rsu_copy_dcmf_version(x1, x2); 921 SMC_RET1(handle, status); 922 923 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO: 924 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf, 925 ARRAY_SIZE(rsu_respbuf)); 926 if (status) { 927 SMC_RET1(handle, status); 928 } else { 929 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1], 930 rsu_respbuf[2], rsu_respbuf[3]); 931 } 932 933 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 934 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 935 ((uint64_t)rsu_dcmf_stat[3] << 48) | 936 ((uint64_t)rsu_dcmf_stat[2] << 32) | 937 ((uint64_t)rsu_dcmf_stat[1] << 16) | 938 rsu_dcmf_stat[0]); 939 940 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 941 status = intel_rsu_copy_dcmf_status(x1); 942 SMC_RET1(handle, status); 943 944 case INTEL_SIP_SMC_RSU_MAX_RETRY: 945 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 946 947 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 948 rsu_max_retry = x1; 949 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 950 951 case INTEL_SIP_SMC_ECC_DBE: 952 status = intel_ecc_dbe_notification(x1); 953 SMC_RET1(handle, status); 954 955 case INTEL_SIP_SMC_SERVICE_COMPLETED: 956 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 957 &len_in_resp, &mbox_error); 958 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 959 960 case INTEL_SIP_SMC_FIRMWARE_VERSION: 961 status = intel_smc_fw_version(&retval); 962 SMC_RET2(handle, status, retval); 963 964 case INTEL_SIP_SMC_MBOX_SEND_CMD: 965 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 966 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 967 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 968 &mbox_status, &len_in_resp); 969 SMC_RET3(handle, status, mbox_status, len_in_resp); 970 971 case INTEL_SIP_SMC_GET_USERCODE: 972 status = intel_smc_get_usercode(&retval); 973 SMC_RET2(handle, status, retval); 974 975 case INTEL_SIP_SMC_FCS_CRYPTION: 976 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 977 978 if (x1 == FCS_MODE_DECRYPT) { 979 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 980 } else if (x1 == FCS_MODE_ENCRYPT) { 981 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 982 } else { 983 status = INTEL_SIP_SMC_STATUS_REJECTED; 984 } 985 986 SMC_RET3(handle, status, x4, x5); 987 988 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 989 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 990 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 991 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 992 993 if (x3 == FCS_MODE_DECRYPT) { 994 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 995 (uint32_t *) &x7, &mbox_error); 996 } else if (x3 == FCS_MODE_ENCRYPT) { 997 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 998 (uint32_t *) &x7, &mbox_error); 999 } else { 1000 status = INTEL_SIP_SMC_STATUS_REJECTED; 1001 } 1002 1003 SMC_RET4(handle, status, mbox_error, x6, x7); 1004 1005 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 1006 status = intel_fcs_random_number_gen(x1, &retval64, 1007 &mbox_error); 1008 SMC_RET4(handle, status, mbox_error, x1, retval64); 1009 1010 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 1011 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 1012 &send_id); 1013 SMC_RET1(handle, status); 1014 1015 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 1016 status = intel_fcs_send_cert(x1, x2, &send_id); 1017 SMC_RET1(handle, status); 1018 1019 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 1020 status = intel_fcs_get_provision_data(&send_id); 1021 SMC_RET1(handle, status); 1022 1023 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 1024 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 1025 &mbox_error); 1026 SMC_RET2(handle, status, mbox_error); 1027 1028 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 1029 status = intel_hps_set_bridges(x1, x2); 1030 SMC_RET1(handle, status); 1031 1032 case INTEL_SIP_SMC_HWMON_READTEMP: 1033 status = intel_hwmon_readtemp(x1, &retval); 1034 SMC_RET2(handle, status, retval); 1035 1036 case INTEL_SIP_SMC_HWMON_READVOLT: 1037 status = intel_hwmon_readvolt(x1, &retval); 1038 SMC_RET2(handle, status, retval); 1039 1040 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 1041 status = intel_fcs_sigma_teardown(x1, &mbox_error); 1042 SMC_RET2(handle, status, mbox_error); 1043 1044 case INTEL_SIP_SMC_FCS_CHIP_ID: 1045 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 1046 SMC_RET4(handle, status, mbox_error, retval, retval2); 1047 1048 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 1049 status = intel_fcs_attestation_subkey(x1, x2, x3, 1050 (uint32_t *) &x4, &mbox_error); 1051 SMC_RET4(handle, status, mbox_error, x3, x4); 1052 1053 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 1054 status = intel_fcs_get_measurement(x1, x2, x3, 1055 (uint32_t *) &x4, &mbox_error); 1056 SMC_RET4(handle, status, mbox_error, x3, x4); 1057 1058 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 1059 status = intel_fcs_get_attestation_cert(x1, x2, 1060 (uint32_t *) &x3, &mbox_error); 1061 SMC_RET4(handle, status, mbox_error, x2, x3); 1062 1063 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 1064 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 1065 SMC_RET2(handle, status, mbox_error); 1066 1067 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 1068 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 1069 SMC_RET3(handle, status, mbox_error, retval); 1070 1071 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 1072 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 1073 SMC_RET2(handle, status, mbox_error); 1074 1075 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 1076 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 1077 SMC_RET1(handle, status); 1078 1079 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 1080 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 1081 (uint32_t *) &x4, &mbox_error); 1082 SMC_RET4(handle, status, mbox_error, x3, x4); 1083 1084 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 1085 status = intel_fcs_remove_crypto_service_key(x1, x2, 1086 &mbox_error); 1087 SMC_RET2(handle, status, mbox_error); 1088 1089 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 1090 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 1091 (uint32_t *) &x4, &mbox_error); 1092 SMC_RET4(handle, status, mbox_error, x3, x4); 1093 1094 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 1095 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1096 status = intel_fcs_get_digest_init(x1, x2, x3, 1097 x4, x5, &mbox_error); 1098 SMC_RET2(handle, status, mbox_error); 1099 1100 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 1101 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1102 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1103 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1104 x4, x5, (uint32_t *) &x6, false, 1105 &mbox_error); 1106 SMC_RET4(handle, status, mbox_error, x5, x6); 1107 1108 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 1109 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1110 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1111 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1112 x4, x5, (uint32_t *) &x6, true, 1113 &mbox_error); 1114 SMC_RET4(handle, status, mbox_error, x5, x6); 1115 1116 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 1117 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1118 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1119 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1120 x4, x5, (uint32_t *) &x6, false, 1121 &mbox_error, &send_id); 1122 SMC_RET4(handle, status, mbox_error, x5, x6); 1123 1124 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 1125 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1126 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1127 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1128 x4, x5, (uint32_t *) &x6, true, 1129 &mbox_error, &send_id); 1130 SMC_RET4(handle, status, mbox_error, x5, x6); 1131 1132 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 1133 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1134 status = intel_fcs_mac_verify_init(x1, x2, x3, 1135 x4, x5, &mbox_error); 1136 SMC_RET2(handle, status, mbox_error); 1137 1138 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 1139 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1140 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1141 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1142 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1143 x4, x5, (uint32_t *) &x6, x7, 1144 false, &mbox_error); 1145 SMC_RET4(handle, status, mbox_error, x5, x6); 1146 1147 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 1148 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1149 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1150 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1151 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1152 x4, x5, (uint32_t *) &x6, x7, 1153 true, &mbox_error); 1154 SMC_RET4(handle, status, mbox_error, x5, x6); 1155 1156 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 1157 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1158 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1159 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1160 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1161 x4, x5, (uint32_t *) &x6, x7, 1162 false, &mbox_error, &send_id); 1163 SMC_RET4(handle, status, mbox_error, x5, x6); 1164 1165 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 1166 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1167 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1168 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1169 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1170 x4, x5, (uint32_t *) &x6, x7, 1171 true, &mbox_error, &send_id); 1172 SMC_RET4(handle, status, mbox_error, x5, x6); 1173 1174 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1175 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1176 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 1177 x4, x5, &mbox_error); 1178 SMC_RET2(handle, status, mbox_error); 1179 1180 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1181 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1182 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1183 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1184 x3, x4, x5, (uint32_t *) &x6, false, 1185 &mbox_error); 1186 SMC_RET4(handle, status, mbox_error, x5, x6); 1187 1188 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1189 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1190 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1191 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1192 x3, x4, x5, (uint32_t *) &x6, true, 1193 &mbox_error); 1194 SMC_RET4(handle, status, mbox_error, x5, x6); 1195 1196 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1197 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1198 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1199 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1200 x2, x3, x4, x5, (uint32_t *) &x6, false, 1201 &mbox_error, &send_id); 1202 SMC_RET4(handle, status, mbox_error, x5, x6); 1203 1204 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1205 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1206 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1207 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1208 x2, x3, x4, x5, (uint32_t *) &x6, true, 1209 &mbox_error, &send_id); 1210 SMC_RET4(handle, status, mbox_error, x5, x6); 1211 1212 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 1213 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1214 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 1215 x4, x5, &mbox_error); 1216 SMC_RET2(handle, status, mbox_error); 1217 1218 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1219 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1220 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1221 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 1222 x4, x5, (uint32_t *) &x6, &mbox_error); 1223 SMC_RET4(handle, status, mbox_error, x5, x6); 1224 1225 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1226 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1227 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 1228 x4, x5, &mbox_error); 1229 SMC_RET2(handle, status, mbox_error); 1230 1231 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1232 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1233 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1234 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 1235 x4, x5, (uint32_t *) &x6, &mbox_error); 1236 SMC_RET4(handle, status, mbox_error, x5, x6); 1237 1238 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1239 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1240 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 1241 x4, x5, &mbox_error); 1242 SMC_RET2(handle, status, mbox_error); 1243 1244 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1245 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1246 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1247 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1248 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1249 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1250 x7, false, &mbox_error); 1251 SMC_RET4(handle, status, mbox_error, x5, x6); 1252 1253 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1254 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1255 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1256 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1257 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1258 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1259 x7, false, &mbox_error, &send_id); 1260 SMC_RET4(handle, status, mbox_error, x5, x6); 1261 1262 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1263 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1264 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1265 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1266 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1267 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1268 x7, true, &mbox_error, &send_id); 1269 SMC_RET4(handle, status, mbox_error, x5, x6); 1270 1271 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1272 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1273 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1274 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1275 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1276 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1277 x7, true, &mbox_error); 1278 SMC_RET4(handle, status, mbox_error, x5, x6); 1279 1280 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1281 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1282 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1283 x4, x5, &mbox_error); 1284 SMC_RET2(handle, status, mbox_error); 1285 1286 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1287 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1288 (uint32_t *) &x4, &mbox_error); 1289 SMC_RET4(handle, status, mbox_error, x3, x4); 1290 1291 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1292 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1293 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1294 x4, x5, &mbox_error); 1295 SMC_RET2(handle, status, mbox_error); 1296 1297 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1298 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1299 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1300 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1301 x4, x5, (uint32_t *) &x6, &mbox_error); 1302 SMC_RET4(handle, status, mbox_error, x5, x6); 1303 1304 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1305 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1306 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1307 &mbox_error); 1308 SMC_RET2(handle, status, mbox_error); 1309 1310 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1311 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1312 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1313 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1314 x5, x6, false, &send_id); 1315 SMC_RET1(handle, status); 1316 1317 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1318 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1319 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1320 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1321 x5, x6, true, &send_id); 1322 SMC_RET1(handle, status); 1323 1324 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 1325 case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG: 1326 status = intel_smmu_hps_remapper_config(x1); 1327 SMC_RET1(handle, status); 1328 #endif 1329 1330 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1331 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1332 &mbox_error); 1333 SMC_RET4(handle, status, mbox_error, x1, retval64); 1334 1335 case INTEL_SIP_SMC_SVC_VERSION: 1336 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1337 SIP_SVC_VERSION_MAJOR, 1338 SIP_SVC_VERSION_MINOR); 1339 1340 case INTEL_SIP_SMC_SEU_ERR_STATUS: 1341 status = intel_sdm_seu_err_read(seu_respbuf, 1342 ARRAY_SIZE(seu_respbuf)); 1343 if (status) { 1344 SMC_RET1(handle, status); 1345 } else { 1346 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 1347 } 1348 1349 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 1350 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 1351 SMC_RET1(handle, status); 1352 1353 default: 1354 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1355 cookie, handle, flags); 1356 } 1357 } 1358 1359 uintptr_t sip_smc_handler(uint32_t smc_fid, 1360 u_register_t x1, 1361 u_register_t x2, 1362 u_register_t x3, 1363 u_register_t x4, 1364 void *cookie, 1365 void *handle, 1366 u_register_t flags) 1367 { 1368 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1369 1370 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1371 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1372 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1373 cookie, handle, flags); 1374 } else { 1375 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1376 cookie, handle, flags); 1377 } 1378 } 1379 1380 DECLARE_RT_SVC( 1381 socfpga_sip_svc, 1382 OEN_SIP_START, 1383 OEN_SIP_END, 1384 SMC_TYPE_FAST, 1385 NULL, 1386 sip_smc_handler 1387 ); 1388 1389 DECLARE_RT_SVC( 1390 socfpga_sip_svc_std, 1391 OEN_SIP_START, 1392 OEN_SIP_END, 1393 SMC_TYPE_YIELD, 1394 NULL, 1395 sip_smc_handler 1396 ); 1397