1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <common/debug.h> 11 #include <common/runtime_svc.h> 12 #include <lib/mmio.h> 13 #include <tools_share/uuid.h> 14 15 #include "socfpga_fcs.h" 16 #include "socfpga_mailbox.h" 17 #include "socfpga_plat_def.h" 18 #include "socfpga_reset_manager.h" 19 #include "socfpga_sip_svc.h" 20 #include "socfpga_system_manager.h" 21 22 /* Total buffer the driver can hold */ 23 #define FPGA_CONFIG_BUFFER_SIZE 4 24 25 static config_type request_type = NO_REQUEST; 26 static int current_block, current_buffer; 27 static int read_block, max_blocks; 28 static uint32_t send_id, rcv_id; 29 static uint32_t bytes_per_block, blocks_submitted; 30 static bool bridge_disable; 31 32 /* RSU static variables */ 33 static uint32_t rsu_dcmf_ver[4] = {0}; 34 static uint16_t rsu_dcmf_stat[4] = {0}; 35 static uint32_t rsu_max_retry; 36 37 /* SiP Service UUID */ 38 DEFINE_SVC_UUID2(intl_svc_uid, 39 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 40 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 41 42 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 43 uint64_t x1, 44 uint64_t x2, 45 uint64_t x3, 46 uint64_t x4, 47 void *cookie, 48 void *handle, 49 uint64_t flags) 50 { 51 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 52 SMC_RET1(handle, SMC_UNK); 53 } 54 55 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 56 57 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 58 { 59 uint32_t args[3]; 60 61 while (max_blocks > 0 && buffer->size > buffer->size_written) { 62 args[0] = (1<<8); 63 args[1] = buffer->addr + buffer->size_written; 64 if (buffer->size - buffer->size_written <= bytes_per_block) { 65 args[2] = buffer->size - buffer->size_written; 66 current_buffer++; 67 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 68 } else { 69 args[2] = bytes_per_block; 70 } 71 72 buffer->size_written += args[2]; 73 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 74 3U, CMD_INDIRECT); 75 76 buffer->subblocks_sent++; 77 max_blocks--; 78 } 79 80 return !max_blocks; 81 } 82 83 static int intel_fpga_sdm_write_all(void) 84 { 85 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 86 if (intel_fpga_sdm_write_buffer( 87 &fpga_config_buffers[current_buffer])) { 88 break; 89 } 90 } 91 return 0; 92 } 93 94 static uint32_t intel_mailbox_fpga_config_isdone(void) 95 { 96 uint32_t ret; 97 98 switch (request_type) { 99 case RECONFIGURATION: 100 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 101 true); 102 break; 103 case BITSTREAM_AUTH: 104 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 105 false); 106 break; 107 default: 108 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 109 false); 110 break; 111 } 112 113 if (ret != 0U) { 114 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 115 return INTEL_SIP_SMC_STATUS_BUSY; 116 } else { 117 request_type = NO_REQUEST; 118 return INTEL_SIP_SMC_STATUS_ERROR; 119 } 120 } 121 122 if (bridge_disable != 0U) { 123 socfpga_bridges_enable(~0); /* Enable bridge */ 124 bridge_disable = false; 125 } 126 request_type = NO_REQUEST; 127 128 return INTEL_SIP_SMC_STATUS_OK; 129 } 130 131 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 132 { 133 int i; 134 135 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 136 if (fpga_config_buffers[i].block_number == current_block) { 137 fpga_config_buffers[i].subblocks_sent--; 138 if (fpga_config_buffers[i].subblocks_sent == 0 139 && fpga_config_buffers[i].size <= 140 fpga_config_buffers[i].size_written) { 141 fpga_config_buffers[i].write_requested = 0; 142 current_block++; 143 *buffer_addr_completed = 144 fpga_config_buffers[i].addr; 145 return 0; 146 } 147 } 148 } 149 150 return -1; 151 } 152 153 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 154 uint32_t *count, uint32_t *job_id) 155 { 156 uint32_t resp[5]; 157 unsigned int resp_len = ARRAY_SIZE(resp); 158 int status = INTEL_SIP_SMC_STATUS_OK; 159 int all_completed = 1; 160 *count = 0; 161 162 while (*count < 3) { 163 164 status = mailbox_read_response(job_id, 165 resp, &resp_len); 166 167 if (status < 0) { 168 break; 169 } 170 171 max_blocks++; 172 173 if (mark_last_buffer_xfer_completed( 174 &completed_addr[*count]) == 0) { 175 *count = *count + 1; 176 } else { 177 break; 178 } 179 } 180 181 if (*count <= 0) { 182 if (status != MBOX_NO_RESPONSE && 183 status != MBOX_TIMEOUT && resp_len != 0) { 184 mailbox_clear_response(); 185 request_type = NO_REQUEST; 186 return INTEL_SIP_SMC_STATUS_ERROR; 187 } 188 189 *count = 0; 190 } 191 192 intel_fpga_sdm_write_all(); 193 194 if (*count > 0) { 195 status = INTEL_SIP_SMC_STATUS_OK; 196 } else if (*count == 0) { 197 status = INTEL_SIP_SMC_STATUS_BUSY; 198 } 199 200 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 201 if (fpga_config_buffers[i].write_requested != 0) { 202 all_completed = 0; 203 break; 204 } 205 } 206 207 if (all_completed == 1) { 208 return INTEL_SIP_SMC_STATUS_OK; 209 } 210 211 return status; 212 } 213 214 static int intel_fpga_config_start(uint32_t flag) 215 { 216 uint32_t argument = 0x1; 217 uint32_t response[3]; 218 int status = 0; 219 unsigned int size = 0; 220 unsigned int resp_len = ARRAY_SIZE(response); 221 222 request_type = RECONFIGURATION; 223 224 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 225 bridge_disable = true; 226 } 227 228 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 229 size = 1; 230 bridge_disable = false; 231 request_type = BITSTREAM_AUTH; 232 } 233 234 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 235 intel_smmu_hps_remapper_init(0U); 236 #endif 237 238 mailbox_clear_response(); 239 240 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 241 CMD_CASUAL, NULL, NULL); 242 243 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 244 CMD_CASUAL, response, &resp_len); 245 246 if (status < 0) { 247 bridge_disable = false; 248 request_type = NO_REQUEST; 249 return INTEL_SIP_SMC_STATUS_ERROR; 250 } 251 252 max_blocks = response[0]; 253 bytes_per_block = response[1]; 254 255 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 256 fpga_config_buffers[i].size = 0; 257 fpga_config_buffers[i].size_written = 0; 258 fpga_config_buffers[i].addr = 0; 259 fpga_config_buffers[i].write_requested = 0; 260 fpga_config_buffers[i].block_number = 0; 261 fpga_config_buffers[i].subblocks_sent = 0; 262 } 263 264 blocks_submitted = 0; 265 current_block = 0; 266 read_block = 0; 267 current_buffer = 0; 268 269 /* Disable bridge on full reconfiguration */ 270 if (bridge_disable) { 271 socfpga_bridges_disable(~0); 272 } 273 274 return INTEL_SIP_SMC_STATUS_OK; 275 } 276 277 static bool is_fpga_config_buffer_full(void) 278 { 279 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 280 if (!fpga_config_buffers[i].write_requested) { 281 return false; 282 } 283 } 284 return true; 285 } 286 287 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 288 { 289 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 290 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 291 292 if (!addr && !size) { 293 return true; 294 } 295 if (size > (UINT64_MAX - addr)) { 296 return false; 297 } 298 if (addr < BL31_LIMIT) { 299 return false; 300 } 301 if (dram_region_end > dram_max_sz) { 302 return false; 303 } 304 305 return true; 306 } 307 308 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 309 { 310 int i; 311 312 intel_fpga_sdm_write_all(); 313 314 if (!is_address_in_ddr_range(mem, size) || 315 is_fpga_config_buffer_full()) { 316 return INTEL_SIP_SMC_STATUS_REJECTED; 317 } 318 319 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 320 intel_smmu_hps_remapper_init(&mem); 321 #endif 322 323 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 324 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 325 326 if (!fpga_config_buffers[j].write_requested) { 327 fpga_config_buffers[j].addr = mem; 328 fpga_config_buffers[j].size = size; 329 fpga_config_buffers[j].size_written = 0; 330 fpga_config_buffers[j].write_requested = 1; 331 fpga_config_buffers[j].block_number = 332 blocks_submitted++; 333 fpga_config_buffers[j].subblocks_sent = 0; 334 break; 335 } 336 } 337 338 if (is_fpga_config_buffer_full()) { 339 return INTEL_SIP_SMC_STATUS_BUSY; 340 } 341 342 return INTEL_SIP_SMC_STATUS_OK; 343 } 344 345 static int is_out_of_sec_range(uint64_t reg_addr) 346 { 347 #if DEBUG 348 return 0; 349 #endif 350 351 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 352 switch (reg_addr) { 353 case(0xF8011100): /* ECCCTRL1 */ 354 case(0xF8011104): /* ECCCTRL2 */ 355 case(0xF8011110): /* ERRINTEN */ 356 case(0xF8011114): /* ERRINTENS */ 357 case(0xF8011118): /* ERRINTENR */ 358 case(0xF801111C): /* INTMODE */ 359 case(0xF8011120): /* INTSTAT */ 360 case(0xF8011124): /* DIAGINTTEST */ 361 case(0xF801112C): /* DERRADDRA */ 362 case(0xFA000000): /* SMMU SCR0 */ 363 case(0xFA000004): /* SMMU SCR1 */ 364 case(0xFA000400): /* SMMU NSCR0 */ 365 case(0xFA004000): /* SMMU SSD0_REG */ 366 case(0xFA000820): /* SMMU SMR8 */ 367 case(0xFA000c20): /* SMMU SCR8 */ 368 case(0xFA028000): /* SMMU CB8_SCTRL */ 369 case(0xFA001020): /* SMMU CBAR8 */ 370 case(0xFA028030): /* SMMU TCR_LPAE */ 371 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 372 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 373 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 374 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 375 case(0xFA028010): /* SMMU_CB8)TCR2 */ 376 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 377 case(0xFA001820): /* SMMU_CBA2R8 */ 378 case(0xFA000074): /* SMMU_STLBGSTATUS */ 379 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 380 case(0xFA000060): /* SMMU_STLBIALL */ 381 case(0xFA000070): /* SMMU_STLBGSYNC */ 382 case(0xFA028618): /* CB8_TLBALL */ 383 case(0xFA0287F0): /* CB8_TLBSYNC */ 384 case(0xFFD12028): /* SDMMCGRP_CTRL */ 385 case(0xFFD12044): /* EMAC0 */ 386 case(0xFFD12048): /* EMAC1 */ 387 case(0xFFD1204C): /* EMAC2 */ 388 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 389 case(0xFFD12094): /* ECC_INT_MASK_SET */ 390 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 391 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 392 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 393 case(0xFFD120C0): /* NOC_TIMEOUT */ 394 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 395 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 396 case(0xFFD120D0): /* NOC_IDLEACK */ 397 case(0xFFD120D4): /* NOC_IDLESTATUS */ 398 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 399 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 400 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 401 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 402 return 0; 403 #else 404 switch (reg_addr) { 405 406 case(0xF8011104): /* ECCCTRL2 */ 407 case(0xFFD12028): /* SDMMCGRP_CTRL */ 408 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 409 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 410 case(0xFFD120D0): /* NOC_IDLEACK */ 411 412 413 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 414 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 415 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 416 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 417 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 418 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 419 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 420 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 421 422 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */ 423 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 424 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 425 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 426 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 427 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 428 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 429 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 430 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 431 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 432 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 433 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 434 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 435 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 436 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 437 #endif 438 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 439 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 440 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 441 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 442 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 443 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 444 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 445 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 446 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 447 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 448 return 0; 449 450 default: 451 break; 452 } 453 454 return -1; 455 } 456 457 /* Secure register access */ 458 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 459 { 460 if (is_out_of_sec_range(reg_addr)) { 461 return INTEL_SIP_SMC_STATUS_ERROR; 462 } 463 464 *retval = mmio_read_32(reg_addr); 465 466 return INTEL_SIP_SMC_STATUS_OK; 467 } 468 469 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 470 uint32_t *retval) 471 { 472 if (is_out_of_sec_range(reg_addr)) { 473 return INTEL_SIP_SMC_STATUS_ERROR; 474 } 475 476 switch (reg_addr) { 477 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 478 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 479 mmio_write_16(reg_addr, val); 480 break; 481 default: 482 mmio_write_32(reg_addr, val); 483 break; 484 } 485 486 return intel_secure_reg_read(reg_addr, retval); 487 } 488 489 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 490 uint32_t val, uint32_t *retval) 491 { 492 if (!intel_secure_reg_read(reg_addr, retval)) { 493 *retval &= ~mask; 494 *retval |= val & mask; 495 return intel_secure_reg_write(reg_addr, *retval, retval); 496 } 497 498 return INTEL_SIP_SMC_STATUS_ERROR; 499 } 500 501 /* Intel Remote System Update (RSU) services */ 502 uint64_t intel_rsu_update_address; 503 504 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 505 { 506 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 507 return INTEL_SIP_SMC_RSU_ERROR; 508 } 509 510 return INTEL_SIP_SMC_STATUS_OK; 511 } 512 513 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf, 514 unsigned int respbuf_sz) 515 { 516 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) { 517 return INTEL_SIP_SMC_RSU_ERROR; 518 } 519 520 return INTEL_SIP_SMC_STATUS_OK; 521 } 522 523 uint32_t intel_rsu_update(uint64_t update_address) 524 { 525 if (update_address > SIZE_MAX) { 526 return INTEL_SIP_SMC_STATUS_REJECTED; 527 } 528 529 intel_rsu_update_address = update_address; 530 return INTEL_SIP_SMC_STATUS_OK; 531 } 532 533 static uint32_t intel_rsu_notify(uint32_t execution_stage) 534 { 535 if (mailbox_hps_stage_notify(execution_stage) < 0) { 536 return INTEL_SIP_SMC_RSU_ERROR; 537 } 538 539 return INTEL_SIP_SMC_STATUS_OK; 540 } 541 542 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 543 uint32_t *ret_stat) 544 { 545 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 546 return INTEL_SIP_SMC_RSU_ERROR; 547 } 548 549 *ret_stat = respbuf[8]; 550 return INTEL_SIP_SMC_STATUS_OK; 551 } 552 553 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 554 uint64_t dcmf_ver_3_2) 555 { 556 rsu_dcmf_ver[0] = dcmf_ver_1_0; 557 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 558 rsu_dcmf_ver[2] = dcmf_ver_3_2; 559 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 560 561 return INTEL_SIP_SMC_STATUS_OK; 562 } 563 564 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 565 { 566 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 567 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 568 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 569 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 570 571 return INTEL_SIP_SMC_STATUS_OK; 572 } 573 574 /* Intel HWMON services */ 575 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 576 { 577 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 578 return INTEL_SIP_SMC_STATUS_ERROR; 579 } 580 581 return INTEL_SIP_SMC_STATUS_OK; 582 } 583 584 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 585 { 586 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 587 return INTEL_SIP_SMC_STATUS_ERROR; 588 } 589 590 return INTEL_SIP_SMC_STATUS_OK; 591 } 592 593 /* Mailbox services */ 594 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 595 { 596 int status; 597 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 598 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 599 600 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 601 CMD_CASUAL, resp_data, &resp_len); 602 603 if (status < 0) { 604 return INTEL_SIP_SMC_STATUS_ERROR; 605 } 606 607 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 608 return INTEL_SIP_SMC_STATUS_ERROR; 609 } 610 611 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 612 613 return INTEL_SIP_SMC_STATUS_OK; 614 } 615 616 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 617 unsigned int len, uint32_t urgent, uint64_t response, 618 unsigned int resp_len, int *mbox_status, 619 unsigned int *len_in_resp) 620 { 621 *len_in_resp = 0; 622 *mbox_status = GENERIC_RESPONSE_ERROR; 623 624 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 625 return INTEL_SIP_SMC_STATUS_REJECTED; 626 } 627 628 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 629 (uint32_t *) response, &resp_len); 630 631 if (status < 0) { 632 *mbox_status = -status; 633 return INTEL_SIP_SMC_STATUS_ERROR; 634 } 635 636 *mbox_status = 0; 637 *len_in_resp = resp_len; 638 639 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 640 641 return INTEL_SIP_SMC_STATUS_OK; 642 } 643 644 static int intel_smc_get_usercode(uint32_t *user_code) 645 { 646 int status; 647 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 648 649 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 650 0U, CMD_CASUAL, user_code, &resp_len); 651 652 if (status < 0) { 653 return INTEL_SIP_SMC_STATUS_ERROR; 654 } 655 656 return INTEL_SIP_SMC_STATUS_OK; 657 } 658 659 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 660 uint32_t mode, uint32_t *job_id, 661 uint32_t *ret_size, uint32_t *mbox_error) 662 { 663 int status = 0; 664 uint32_t resp_len = size / MBOX_WORD_BYTE; 665 666 if (resp_len > MBOX_DATA_MAX_LEN) { 667 return INTEL_SIP_SMC_STATUS_REJECTED; 668 } 669 670 if (!is_address_in_ddr_range(addr, size)) { 671 return INTEL_SIP_SMC_STATUS_REJECTED; 672 } 673 674 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 675 status = mailbox_read_response_async(job_id, 676 NULL, (uint32_t *) addr, &resp_len, 0); 677 } else { 678 status = mailbox_read_response(job_id, 679 (uint32_t *) addr, &resp_len); 680 681 if (status == MBOX_NO_RESPONSE) { 682 status = MBOX_BUSY; 683 } 684 } 685 686 if (status == MBOX_NO_RESPONSE) { 687 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 688 } 689 690 if (status == MBOX_BUSY) { 691 return INTEL_SIP_SMC_STATUS_BUSY; 692 } 693 694 *ret_size = resp_len * MBOX_WORD_BYTE; 695 flush_dcache_range(addr, *ret_size); 696 697 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 698 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 699 *mbox_error = -status; 700 } else if (status != MBOX_RET_OK) { 701 *mbox_error = -status; 702 return INTEL_SIP_SMC_STATUS_ERROR; 703 } 704 705 return INTEL_SIP_SMC_STATUS_OK; 706 } 707 708 /* Miscellaneous HPS services */ 709 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 710 { 711 int status = 0; 712 713 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 714 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 715 status = socfpga_bridges_enable((uint32_t)mask); 716 } else { 717 status = socfpga_bridges_enable(~0); 718 } 719 } else { 720 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 721 status = socfpga_bridges_disable((uint32_t)mask); 722 } else { 723 status = socfpga_bridges_disable(~0); 724 } 725 } 726 727 if (status < 0) { 728 return INTEL_SIP_SMC_STATUS_ERROR; 729 } 730 731 return INTEL_SIP_SMC_STATUS_OK; 732 } 733 734 /* SDM SEU Error services */ 735 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 736 { 737 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 738 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 739 } 740 741 return INTEL_SIP_SMC_STATUS_OK; 742 } 743 744 /* SDM SAFE SEU Error inject services */ 745 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 746 { 747 if (mailbox_safe_inject_seu_err(command, len) < 0) { 748 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 749 } 750 751 return INTEL_SIP_SMC_STATUS_OK; 752 } 753 754 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 755 /* SMMU HPS Remapper */ 756 void intel_smmu_hps_remapper_init(uint64_t *mem) 757 { 758 /* Read out Bit 1 value */ 759 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 760 761 if (remap == 0x00) { 762 /* Update DRAM Base address for SDM SMMU */ 763 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 764 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 765 *mem = *mem - DRAM_BASE; 766 } else { 767 *mem = *mem - DRAM_BASE; 768 } 769 } 770 #endif 771 772 /* 773 * This function is responsible for handling all SiP calls from the NS world 774 */ 775 776 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 777 u_register_t x1, 778 u_register_t x2, 779 u_register_t x3, 780 u_register_t x4, 781 void *cookie, 782 void *handle, 783 u_register_t flags) 784 { 785 uint32_t retval = 0, completed_addr[3]; 786 uint32_t retval2 = 0; 787 uint32_t mbox_error = 0; 788 uint64_t retval64, rsu_respbuf[9]; 789 uint32_t seu_respbuf[3]; 790 int status = INTEL_SIP_SMC_STATUS_OK; 791 int mbox_status; 792 unsigned int len_in_resp; 793 u_register_t x5, x6, x7; 794 795 switch (smc_fid) { 796 case SIP_SVC_UID: 797 /* Return UID to the caller */ 798 SMC_UUID_RET(handle, intl_svc_uid); 799 800 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 801 status = intel_mailbox_fpga_config_isdone(); 802 SMC_RET4(handle, status, 0, 0, 0); 803 804 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 805 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 806 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 807 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 808 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 809 810 case INTEL_SIP_SMC_FPGA_CONFIG_START: 811 status = intel_fpga_config_start(x1); 812 SMC_RET4(handle, status, 0, 0, 0); 813 814 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 815 status = intel_fpga_config_write(x1, x2); 816 SMC_RET4(handle, status, 0, 0, 0); 817 818 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 819 status = intel_fpga_config_completed_write(completed_addr, 820 &retval, &rcv_id); 821 switch (retval) { 822 case 1: 823 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 824 completed_addr[0], 0, 0); 825 826 case 2: 827 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 828 completed_addr[0], 829 completed_addr[1], 0); 830 831 case 3: 832 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 833 completed_addr[0], 834 completed_addr[1], 835 completed_addr[2]); 836 837 case 0: 838 SMC_RET4(handle, status, 0, 0, 0); 839 840 default: 841 mailbox_clear_response(); 842 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 843 } 844 845 case INTEL_SIP_SMC_REG_READ: 846 status = intel_secure_reg_read(x1, &retval); 847 SMC_RET3(handle, status, retval, x1); 848 849 case INTEL_SIP_SMC_REG_WRITE: 850 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 851 SMC_RET3(handle, status, retval, x1); 852 853 case INTEL_SIP_SMC_REG_UPDATE: 854 status = intel_secure_reg_update(x1, (uint32_t)x2, 855 (uint32_t)x3, &retval); 856 SMC_RET3(handle, status, retval, x1); 857 858 case INTEL_SIP_SMC_RSU_STATUS: 859 status = intel_rsu_status(rsu_respbuf, 860 ARRAY_SIZE(rsu_respbuf)); 861 if (status) { 862 SMC_RET1(handle, status); 863 } else { 864 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 865 rsu_respbuf[2], rsu_respbuf[3]); 866 } 867 868 case INTEL_SIP_SMC_RSU_UPDATE: 869 status = intel_rsu_update(x1); 870 SMC_RET1(handle, status); 871 872 case INTEL_SIP_SMC_RSU_NOTIFY: 873 status = intel_rsu_notify(x1); 874 SMC_RET1(handle, status); 875 876 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 877 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 878 ARRAY_SIZE(rsu_respbuf), &retval); 879 if (status) { 880 SMC_RET1(handle, status); 881 } else { 882 SMC_RET2(handle, status, retval); 883 } 884 885 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 886 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 887 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 888 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 889 890 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 891 status = intel_rsu_copy_dcmf_version(x1, x2); 892 SMC_RET1(handle, status); 893 894 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO: 895 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf, 896 ARRAY_SIZE(rsu_respbuf)); 897 if (status) { 898 SMC_RET1(handle, status); 899 } else { 900 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1], 901 rsu_respbuf[2], rsu_respbuf[3]); 902 } 903 904 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 905 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 906 ((uint64_t)rsu_dcmf_stat[3] << 48) | 907 ((uint64_t)rsu_dcmf_stat[2] << 32) | 908 ((uint64_t)rsu_dcmf_stat[1] << 16) | 909 rsu_dcmf_stat[0]); 910 911 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 912 status = intel_rsu_copy_dcmf_status(x1); 913 SMC_RET1(handle, status); 914 915 case INTEL_SIP_SMC_RSU_MAX_RETRY: 916 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 917 918 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 919 rsu_max_retry = x1; 920 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 921 922 case INTEL_SIP_SMC_ECC_DBE: 923 status = intel_ecc_dbe_notification(x1); 924 SMC_RET1(handle, status); 925 926 case INTEL_SIP_SMC_SERVICE_COMPLETED: 927 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 928 &len_in_resp, &mbox_error); 929 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 930 931 case INTEL_SIP_SMC_FIRMWARE_VERSION: 932 status = intel_smc_fw_version(&retval); 933 SMC_RET2(handle, status, retval); 934 935 case INTEL_SIP_SMC_MBOX_SEND_CMD: 936 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 937 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 938 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 939 &mbox_status, &len_in_resp); 940 SMC_RET3(handle, status, mbox_status, len_in_resp); 941 942 case INTEL_SIP_SMC_GET_USERCODE: 943 status = intel_smc_get_usercode(&retval); 944 SMC_RET2(handle, status, retval); 945 946 case INTEL_SIP_SMC_FCS_CRYPTION: 947 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 948 949 if (x1 == FCS_MODE_DECRYPT) { 950 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 951 } else if (x1 == FCS_MODE_ENCRYPT) { 952 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 953 } else { 954 status = INTEL_SIP_SMC_STATUS_REJECTED; 955 } 956 957 SMC_RET3(handle, status, x4, x5); 958 959 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 960 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 961 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 962 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 963 964 if (x3 == FCS_MODE_DECRYPT) { 965 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 966 (uint32_t *) &x7, &mbox_error); 967 } else if (x3 == FCS_MODE_ENCRYPT) { 968 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 969 (uint32_t *) &x7, &mbox_error); 970 } else { 971 status = INTEL_SIP_SMC_STATUS_REJECTED; 972 } 973 974 SMC_RET4(handle, status, mbox_error, x6, x7); 975 976 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 977 status = intel_fcs_random_number_gen(x1, &retval64, 978 &mbox_error); 979 SMC_RET4(handle, status, mbox_error, x1, retval64); 980 981 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 982 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 983 &send_id); 984 SMC_RET1(handle, status); 985 986 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 987 status = intel_fcs_send_cert(x1, x2, &send_id); 988 SMC_RET1(handle, status); 989 990 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 991 status = intel_fcs_get_provision_data(&send_id); 992 SMC_RET1(handle, status); 993 994 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 995 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 996 &mbox_error); 997 SMC_RET2(handle, status, mbox_error); 998 999 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 1000 status = intel_hps_set_bridges(x1, x2); 1001 SMC_RET1(handle, status); 1002 1003 case INTEL_SIP_SMC_HWMON_READTEMP: 1004 status = intel_hwmon_readtemp(x1, &retval); 1005 SMC_RET2(handle, status, retval); 1006 1007 case INTEL_SIP_SMC_HWMON_READVOLT: 1008 status = intel_hwmon_readvolt(x1, &retval); 1009 SMC_RET2(handle, status, retval); 1010 1011 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 1012 status = intel_fcs_sigma_teardown(x1, &mbox_error); 1013 SMC_RET2(handle, status, mbox_error); 1014 1015 case INTEL_SIP_SMC_FCS_CHIP_ID: 1016 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 1017 SMC_RET4(handle, status, mbox_error, retval, retval2); 1018 1019 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 1020 status = intel_fcs_attestation_subkey(x1, x2, x3, 1021 (uint32_t *) &x4, &mbox_error); 1022 SMC_RET4(handle, status, mbox_error, x3, x4); 1023 1024 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 1025 status = intel_fcs_get_measurement(x1, x2, x3, 1026 (uint32_t *) &x4, &mbox_error); 1027 SMC_RET4(handle, status, mbox_error, x3, x4); 1028 1029 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 1030 status = intel_fcs_get_attestation_cert(x1, x2, 1031 (uint32_t *) &x3, &mbox_error); 1032 SMC_RET4(handle, status, mbox_error, x2, x3); 1033 1034 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 1035 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 1036 SMC_RET2(handle, status, mbox_error); 1037 1038 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 1039 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 1040 SMC_RET3(handle, status, mbox_error, retval); 1041 1042 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 1043 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 1044 SMC_RET2(handle, status, mbox_error); 1045 1046 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 1047 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 1048 SMC_RET1(handle, status); 1049 1050 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 1051 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 1052 (uint32_t *) &x4, &mbox_error); 1053 SMC_RET4(handle, status, mbox_error, x3, x4); 1054 1055 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 1056 status = intel_fcs_remove_crypto_service_key(x1, x2, 1057 &mbox_error); 1058 SMC_RET2(handle, status, mbox_error); 1059 1060 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 1061 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 1062 (uint32_t *) &x4, &mbox_error); 1063 SMC_RET4(handle, status, mbox_error, x3, x4); 1064 1065 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 1066 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1067 status = intel_fcs_get_digest_init(x1, x2, x3, 1068 x4, x5, &mbox_error); 1069 SMC_RET2(handle, status, mbox_error); 1070 1071 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 1072 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1073 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1074 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1075 x4, x5, (uint32_t *) &x6, false, 1076 &mbox_error); 1077 SMC_RET4(handle, status, mbox_error, x5, x6); 1078 1079 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 1080 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1081 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1082 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1083 x4, x5, (uint32_t *) &x6, true, 1084 &mbox_error); 1085 SMC_RET4(handle, status, mbox_error, x5, x6); 1086 1087 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 1088 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1089 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1090 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1091 x4, x5, (uint32_t *) &x6, false, 1092 &mbox_error, &send_id); 1093 SMC_RET4(handle, status, mbox_error, x5, x6); 1094 1095 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 1096 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1097 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1098 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1099 x4, x5, (uint32_t *) &x6, true, 1100 &mbox_error, &send_id); 1101 SMC_RET4(handle, status, mbox_error, x5, x6); 1102 1103 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 1104 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1105 status = intel_fcs_mac_verify_init(x1, x2, x3, 1106 x4, x5, &mbox_error); 1107 SMC_RET2(handle, status, mbox_error); 1108 1109 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 1110 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1111 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1112 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1113 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1114 x4, x5, (uint32_t *) &x6, x7, 1115 false, &mbox_error); 1116 SMC_RET4(handle, status, mbox_error, x5, x6); 1117 1118 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 1119 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1120 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1121 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1122 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1123 x4, x5, (uint32_t *) &x6, x7, 1124 true, &mbox_error); 1125 SMC_RET4(handle, status, mbox_error, x5, x6); 1126 1127 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 1128 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1129 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1130 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1131 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1132 x4, x5, (uint32_t *) &x6, x7, 1133 false, &mbox_error, &send_id); 1134 SMC_RET4(handle, status, mbox_error, x5, x6); 1135 1136 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 1137 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1138 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1139 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1140 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1141 x4, x5, (uint32_t *) &x6, x7, 1142 true, &mbox_error, &send_id); 1143 SMC_RET4(handle, status, mbox_error, x5, x6); 1144 1145 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1146 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1147 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 1148 x4, x5, &mbox_error); 1149 SMC_RET2(handle, status, mbox_error); 1150 1151 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1152 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1153 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1154 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1155 x3, x4, x5, (uint32_t *) &x6, false, 1156 &mbox_error); 1157 SMC_RET4(handle, status, mbox_error, x5, x6); 1158 1159 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1160 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1161 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1162 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1163 x3, x4, x5, (uint32_t *) &x6, true, 1164 &mbox_error); 1165 SMC_RET4(handle, status, mbox_error, x5, x6); 1166 1167 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1168 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1169 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1170 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1171 x2, x3, x4, x5, (uint32_t *) &x6, false, 1172 &mbox_error, &send_id); 1173 SMC_RET4(handle, status, mbox_error, x5, x6); 1174 1175 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1176 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1177 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1178 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1179 x2, x3, x4, x5, (uint32_t *) &x6, true, 1180 &mbox_error, &send_id); 1181 SMC_RET4(handle, status, mbox_error, x5, x6); 1182 1183 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 1184 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1185 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 1186 x4, x5, &mbox_error); 1187 SMC_RET2(handle, status, mbox_error); 1188 1189 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1190 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1191 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1192 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 1193 x4, x5, (uint32_t *) &x6, &mbox_error); 1194 SMC_RET4(handle, status, mbox_error, x5, x6); 1195 1196 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1197 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1198 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 1199 x4, x5, &mbox_error); 1200 SMC_RET2(handle, status, mbox_error); 1201 1202 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1203 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1204 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1205 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 1206 x4, x5, (uint32_t *) &x6, &mbox_error); 1207 SMC_RET4(handle, status, mbox_error, x5, x6); 1208 1209 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1210 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1211 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 1212 x4, x5, &mbox_error); 1213 SMC_RET2(handle, status, mbox_error); 1214 1215 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1216 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1217 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1218 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1219 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1220 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1221 x7, false, &mbox_error); 1222 SMC_RET4(handle, status, mbox_error, x5, x6); 1223 1224 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1225 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1226 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1227 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1228 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1229 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1230 x7, false, &mbox_error, &send_id); 1231 SMC_RET4(handle, status, mbox_error, x5, x6); 1232 1233 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1234 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1235 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1236 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1237 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1238 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1239 x7, true, &mbox_error, &send_id); 1240 SMC_RET4(handle, status, mbox_error, x5, x6); 1241 1242 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1243 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1244 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1245 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1246 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1247 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1248 x7, true, &mbox_error); 1249 SMC_RET4(handle, status, mbox_error, x5, x6); 1250 1251 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1252 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1253 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1254 x4, x5, &mbox_error); 1255 SMC_RET2(handle, status, mbox_error); 1256 1257 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1258 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1259 (uint32_t *) &x4, &mbox_error); 1260 SMC_RET4(handle, status, mbox_error, x3, x4); 1261 1262 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1263 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1264 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1265 x4, x5, &mbox_error); 1266 SMC_RET2(handle, status, mbox_error); 1267 1268 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1269 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1270 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1271 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1272 x4, x5, (uint32_t *) &x6, &mbox_error); 1273 SMC_RET4(handle, status, mbox_error, x5, x6); 1274 1275 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1276 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1277 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1278 &mbox_error); 1279 SMC_RET2(handle, status, mbox_error); 1280 1281 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1282 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1283 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1284 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1285 x5, x6, false, &send_id); 1286 SMC_RET1(handle, status); 1287 1288 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1289 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1290 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1291 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1292 x5, x6, true, &send_id); 1293 SMC_RET1(handle, status); 1294 1295 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1296 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1297 &mbox_error); 1298 SMC_RET4(handle, status, mbox_error, x1, retval64); 1299 1300 case INTEL_SIP_SMC_SVC_VERSION: 1301 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1302 SIP_SVC_VERSION_MAJOR, 1303 SIP_SVC_VERSION_MINOR); 1304 1305 case INTEL_SIP_SMC_SEU_ERR_STATUS: 1306 status = intel_sdm_seu_err_read(seu_respbuf, 1307 ARRAY_SIZE(seu_respbuf)); 1308 if (status) { 1309 SMC_RET1(handle, status); 1310 } else { 1311 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 1312 } 1313 1314 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 1315 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 1316 SMC_RET1(handle, status); 1317 1318 default: 1319 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1320 cookie, handle, flags); 1321 } 1322 } 1323 1324 uintptr_t sip_smc_handler(uint32_t smc_fid, 1325 u_register_t x1, 1326 u_register_t x2, 1327 u_register_t x3, 1328 u_register_t x4, 1329 void *cookie, 1330 void *handle, 1331 u_register_t flags) 1332 { 1333 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1334 1335 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1336 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1337 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1338 cookie, handle, flags); 1339 } else { 1340 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1341 cookie, handle, flags); 1342 } 1343 } 1344 1345 DECLARE_RT_SVC( 1346 socfpga_sip_svc, 1347 OEN_SIP_START, 1348 OEN_SIP_END, 1349 SMC_TYPE_FAST, 1350 NULL, 1351 sip_smc_handler 1352 ); 1353 1354 DECLARE_RT_SVC( 1355 socfpga_sip_svc_std, 1356 OEN_SIP_START, 1357 OEN_SIP_END, 1358 SMC_TYPE_YIELD, 1359 NULL, 1360 sip_smc_handler 1361 ); 1362