1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_reset_manager.h" 16 #include "socfpga_sip_svc.h" 17 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static int current_block, current_buffer; 23 static int read_block, max_blocks, is_partial_reconfig; 24 static uint32_t send_id, rcv_id; 25 static uint32_t bytes_per_block, blocks_submitted; 26 27 28 /* SiP Service UUID */ 29 DEFINE_SVC_UUID2(intl_svc_uid, 30 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 31 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 32 33 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 34 uint64_t x1, 35 uint64_t x2, 36 uint64_t x3, 37 uint64_t x4, 38 void *cookie, 39 void *handle, 40 uint64_t flags) 41 { 42 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 43 SMC_RET1(handle, SMC_UNK); 44 } 45 46 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 47 48 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 49 { 50 uint32_t args[3]; 51 52 while (max_blocks > 0 && buffer->size > buffer->size_written) { 53 args[0] = (1<<8); 54 args[1] = buffer->addr + buffer->size_written; 55 if (buffer->size - buffer->size_written <= bytes_per_block) { 56 args[2] = buffer->size - buffer->size_written; 57 current_buffer++; 58 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 59 } else 60 args[2] = bytes_per_block; 61 62 buffer->size_written += args[2]; 63 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 64 3U, CMD_INDIRECT); 65 66 buffer->subblocks_sent++; 67 max_blocks--; 68 } 69 70 return !max_blocks; 71 } 72 73 static int intel_fpga_sdm_write_all(void) 74 { 75 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 76 if (intel_fpga_sdm_write_buffer( 77 &fpga_config_buffers[current_buffer])) 78 break; 79 return 0; 80 } 81 82 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) 83 { 84 uint32_t ret; 85 86 if (query_type == 1) 87 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false); 88 else 89 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); 90 91 if (ret) { 92 if (ret == MBOX_CFGSTAT_STATE_CONFIG) 93 return INTEL_SIP_SMC_STATUS_BUSY; 94 else 95 return INTEL_SIP_SMC_STATUS_ERROR; 96 } 97 98 if (query_type != 1) { 99 /* full reconfiguration */ 100 if (!is_partial_reconfig) 101 socfpga_bridges_enable(); /* Enable bridge */ 102 } 103 104 return INTEL_SIP_SMC_STATUS_OK; 105 } 106 107 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 108 { 109 int i; 110 111 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 112 if (fpga_config_buffers[i].block_number == current_block) { 113 fpga_config_buffers[i].subblocks_sent--; 114 if (fpga_config_buffers[i].subblocks_sent == 0 115 && fpga_config_buffers[i].size <= 116 fpga_config_buffers[i].size_written) { 117 fpga_config_buffers[i].write_requested = 0; 118 current_block++; 119 *buffer_addr_completed = 120 fpga_config_buffers[i].addr; 121 return 0; 122 } 123 } 124 } 125 126 return -1; 127 } 128 129 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 130 uint32_t *count, uint32_t *job_id) 131 { 132 uint32_t resp[5]; 133 unsigned int resp_len = ARRAY_SIZE(resp); 134 int status = INTEL_SIP_SMC_STATUS_OK; 135 int all_completed = 1; 136 *count = 0; 137 138 while (*count < 3) { 139 140 status = mailbox_read_response(job_id, 141 resp, &resp_len); 142 143 if (status < 0) { 144 break; 145 } 146 147 max_blocks++; 148 149 if (mark_last_buffer_xfer_completed( 150 &completed_addr[*count]) == 0) { 151 *count = *count + 1; 152 } else { 153 break; 154 } 155 } 156 157 if (*count <= 0) { 158 if (status != MBOX_NO_RESPONSE && 159 status != MBOX_TIMEOUT && resp_len != 0) { 160 mailbox_clear_response(); 161 return INTEL_SIP_SMC_STATUS_ERROR; 162 } 163 164 *count = 0; 165 } 166 167 intel_fpga_sdm_write_all(); 168 169 if (*count > 0) 170 status = INTEL_SIP_SMC_STATUS_OK; 171 else if (*count == 0) 172 status = INTEL_SIP_SMC_STATUS_BUSY; 173 174 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 175 if (fpga_config_buffers[i].write_requested != 0) { 176 all_completed = 0; 177 break; 178 } 179 } 180 181 if (all_completed == 1) 182 return INTEL_SIP_SMC_STATUS_OK; 183 184 return status; 185 } 186 187 static int intel_fpga_config_start(uint32_t config_type) 188 { 189 uint32_t argument = 0x1; 190 uint32_t response[3]; 191 int status = 0; 192 unsigned int size = 0; 193 unsigned int resp_len = ARRAY_SIZE(response); 194 195 is_partial_reconfig = config_type; 196 197 mailbox_clear_response(); 198 199 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 200 CMD_CASUAL, NULL, NULL); 201 202 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 203 CMD_CASUAL, response, &resp_len); 204 205 if (status < 0) 206 return status; 207 208 max_blocks = response[0]; 209 bytes_per_block = response[1]; 210 211 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 212 fpga_config_buffers[i].size = 0; 213 fpga_config_buffers[i].size_written = 0; 214 fpga_config_buffers[i].addr = 0; 215 fpga_config_buffers[i].write_requested = 0; 216 fpga_config_buffers[i].block_number = 0; 217 fpga_config_buffers[i].subblocks_sent = 0; 218 } 219 220 blocks_submitted = 0; 221 current_block = 0; 222 read_block = 0; 223 current_buffer = 0; 224 225 /* full reconfiguration */ 226 if (!is_partial_reconfig) { 227 /* Disable bridge */ 228 socfpga_bridges_disable(); 229 } 230 231 return 0; 232 } 233 234 static bool is_fpga_config_buffer_full(void) 235 { 236 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 237 if (!fpga_config_buffers[i].write_requested) 238 return false; 239 return true; 240 } 241 242 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 243 { 244 if (!addr && !size) { 245 return true; 246 } 247 if (size > (UINT64_MAX - addr)) 248 return false; 249 if (addr < BL31_LIMIT) 250 return false; 251 if (addr + size > DRAM_BASE + DRAM_SIZE) 252 return false; 253 254 return true; 255 } 256 257 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 258 { 259 int i; 260 261 intel_fpga_sdm_write_all(); 262 263 if (!is_address_in_ddr_range(mem, size) || 264 is_fpga_config_buffer_full()) 265 return INTEL_SIP_SMC_STATUS_REJECTED; 266 267 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 268 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 269 270 if (!fpga_config_buffers[j].write_requested) { 271 fpga_config_buffers[j].addr = mem; 272 fpga_config_buffers[j].size = size; 273 fpga_config_buffers[j].size_written = 0; 274 fpga_config_buffers[j].write_requested = 1; 275 fpga_config_buffers[j].block_number = 276 blocks_submitted++; 277 fpga_config_buffers[j].subblocks_sent = 0; 278 break; 279 } 280 } 281 282 if (is_fpga_config_buffer_full()) 283 return INTEL_SIP_SMC_STATUS_BUSY; 284 285 return INTEL_SIP_SMC_STATUS_OK; 286 } 287 288 static int is_out_of_sec_range(uint64_t reg_addr) 289 { 290 switch (reg_addr) { 291 case(0xF8011100): /* ECCCTRL1 */ 292 case(0xF8011104): /* ECCCTRL2 */ 293 case(0xF8011110): /* ERRINTEN */ 294 case(0xF8011114): /* ERRINTENS */ 295 case(0xF8011118): /* ERRINTENR */ 296 case(0xF801111C): /* INTMODE */ 297 case(0xF8011120): /* INTSTAT */ 298 case(0xF8011124): /* DIAGINTTEST */ 299 case(0xF801112C): /* DERRADDRA */ 300 case(0xFFD12028): /* SDMMCGRP_CTRL */ 301 case(0xFFD12044): /* EMAC0 */ 302 case(0xFFD12048): /* EMAC1 */ 303 case(0xFFD1204C): /* EMAC2 */ 304 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 305 case(0xFFD12094): /* ECC_INT_MASK_SET */ 306 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 307 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 308 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 309 case(0xFFD120C0): /* NOC_TIMEOUT */ 310 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 311 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 312 case(0xFFD120D0): /* NOC_IDLEACK */ 313 case(0xFFD120D4): /* NOC_IDLESTATUS */ 314 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 315 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 316 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 317 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 318 return 0; 319 320 default: 321 break; 322 } 323 324 return -1; 325 } 326 327 /* Secure register access */ 328 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 329 { 330 if (is_out_of_sec_range(reg_addr)) 331 return INTEL_SIP_SMC_STATUS_ERROR; 332 333 *retval = mmio_read_32(reg_addr); 334 335 return INTEL_SIP_SMC_STATUS_OK; 336 } 337 338 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 339 uint32_t *retval) 340 { 341 if (is_out_of_sec_range(reg_addr)) 342 return INTEL_SIP_SMC_STATUS_ERROR; 343 344 mmio_write_32(reg_addr, val); 345 346 return intel_secure_reg_read(reg_addr, retval); 347 } 348 349 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 350 uint32_t val, uint32_t *retval) 351 { 352 if (!intel_secure_reg_read(reg_addr, retval)) { 353 *retval &= ~mask; 354 *retval |= val & mask; 355 return intel_secure_reg_write(reg_addr, *retval, retval); 356 } 357 358 return INTEL_SIP_SMC_STATUS_ERROR; 359 } 360 361 /* Intel Remote System Update (RSU) services */ 362 uint64_t intel_rsu_update_address; 363 364 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 365 { 366 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 367 return INTEL_SIP_SMC_RSU_ERROR; 368 369 return INTEL_SIP_SMC_STATUS_OK; 370 } 371 372 static uint32_t intel_rsu_update(uint64_t update_address) 373 { 374 intel_rsu_update_address = update_address; 375 return INTEL_SIP_SMC_STATUS_OK; 376 } 377 378 static uint32_t intel_rsu_notify(uint32_t execution_stage) 379 { 380 if (mailbox_hps_stage_notify(execution_stage) < 0) 381 return INTEL_SIP_SMC_RSU_ERROR; 382 383 return INTEL_SIP_SMC_STATUS_OK; 384 } 385 386 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 387 uint32_t *ret_stat) 388 { 389 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 390 return INTEL_SIP_SMC_RSU_ERROR; 391 392 *ret_stat = respbuf[8]; 393 return INTEL_SIP_SMC_STATUS_OK; 394 } 395 396 /* Mailbox services */ 397 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 398 unsigned int len, 399 uint32_t urgent, uint32_t *response, 400 unsigned int resp_len, int *mbox_status, 401 unsigned int *len_in_resp) 402 { 403 *len_in_resp = 0; 404 *mbox_status = 0; 405 406 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) 407 return INTEL_SIP_SMC_STATUS_REJECTED; 408 409 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 410 response, &resp_len); 411 412 if (status < 0) { 413 *mbox_status = -status; 414 return INTEL_SIP_SMC_STATUS_ERROR; 415 } 416 417 *mbox_status = 0; 418 *len_in_resp = resp_len; 419 return INTEL_SIP_SMC_STATUS_OK; 420 } 421 422 /* 423 * This function is responsible for handling all SiP calls from the NS world 424 */ 425 426 uintptr_t sip_smc_handler(uint32_t smc_fid, 427 u_register_t x1, 428 u_register_t x2, 429 u_register_t x3, 430 u_register_t x4, 431 void *cookie, 432 void *handle, 433 u_register_t flags) 434 { 435 uint32_t retval = 0; 436 uint32_t mbox_error = 0; 437 uint32_t completed_addr[3]; 438 uint64_t retval64, rsu_respbuf[9]; 439 int status = INTEL_SIP_SMC_STATUS_OK; 440 int mbox_status; 441 unsigned int len_in_resp; 442 u_register_t x5, x6; 443 444 switch (smc_fid) { 445 case SIP_SVC_UID: 446 /* Return UID to the caller */ 447 SMC_UUID_RET(handle, intl_svc_uid); 448 449 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 450 status = intel_mailbox_fpga_config_isdone(x1); 451 SMC_RET4(handle, status, 0, 0, 0); 452 453 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 454 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 455 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 456 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 457 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 458 459 case INTEL_SIP_SMC_FPGA_CONFIG_START: 460 status = intel_fpga_config_start(x1); 461 SMC_RET4(handle, status, 0, 0, 0); 462 463 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 464 status = intel_fpga_config_write(x1, x2); 465 SMC_RET4(handle, status, 0, 0, 0); 466 467 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 468 status = intel_fpga_config_completed_write(completed_addr, 469 &retval, &rcv_id); 470 switch (retval) { 471 case 1: 472 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 473 completed_addr[0], 0, 0); 474 475 case 2: 476 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 477 completed_addr[0], 478 completed_addr[1], 0); 479 480 case 3: 481 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 482 completed_addr[0], 483 completed_addr[1], 484 completed_addr[2]); 485 486 case 0: 487 SMC_RET4(handle, status, 0, 0, 0); 488 489 default: 490 mailbox_clear_response(); 491 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 492 } 493 494 case INTEL_SIP_SMC_REG_READ: 495 status = intel_secure_reg_read(x1, &retval); 496 SMC_RET3(handle, status, retval, x1); 497 498 case INTEL_SIP_SMC_REG_WRITE: 499 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 500 SMC_RET3(handle, status, retval, x1); 501 502 case INTEL_SIP_SMC_REG_UPDATE: 503 status = intel_secure_reg_update(x1, (uint32_t)x2, 504 (uint32_t)x3, &retval); 505 SMC_RET3(handle, status, retval, x1); 506 507 case INTEL_SIP_SMC_RSU_STATUS: 508 status = intel_rsu_status(rsu_respbuf, 509 ARRAY_SIZE(rsu_respbuf)); 510 if (status) { 511 SMC_RET1(handle, status); 512 } else { 513 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 514 rsu_respbuf[2], rsu_respbuf[3]); 515 } 516 517 case INTEL_SIP_SMC_RSU_UPDATE: 518 status = intel_rsu_update(x1); 519 SMC_RET1(handle, status); 520 521 case INTEL_SIP_SMC_RSU_NOTIFY: 522 status = intel_rsu_notify(x1); 523 SMC_RET1(handle, status); 524 525 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 526 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 527 ARRAY_SIZE(rsu_respbuf), &retval); 528 if (status) { 529 SMC_RET1(handle, status); 530 } else { 531 SMC_RET2(handle, status, retval); 532 } 533 534 case INTEL_SIP_SMC_ECC_DBE: 535 status = intel_ecc_dbe_notification(x1); 536 SMC_RET1(handle, status); 537 538 case INTEL_SIP_SMC_MBOX_SEND_CMD: 539 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 540 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 541 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, 542 (uint32_t *)x5, x6, &mbox_status, 543 &len_in_resp); 544 SMC_RET3(handle, status, mbox_status, len_in_resp); 545 546 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 547 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 548 &mbox_error); 549 SMC_RET4(handle, status, mbox_error, x1, retval64); 550 551 default: 552 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 553 cookie, handle, flags); 554 } 555 } 556 557 DECLARE_RT_SVC( 558 socfpga_sip_svc, 559 OEN_SIP_START, 560 OEN_SIP_END, 561 SMC_TYPE_FAST, 562 NULL, 563 sip_smc_handler 564 ); 565 566 DECLARE_RT_SVC( 567 socfpga_sip_svc_std, 568 OEN_SIP_START, 569 OEN_SIP_END, 570 SMC_TYPE_YIELD, 571 NULL, 572 sip_smc_handler 573 ); 574