1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_mailbox.h" 14 #include "socfpga_reset_manager.h" 15 #include "socfpga_sip_svc.h" 16 17 /* Number of SiP Calls implemented */ 18 #define SIP_NUM_CALLS 0x3 19 20 /* Total buffer the driver can hold */ 21 #define FPGA_CONFIG_BUFFER_SIZE 4 22 23 static int current_block; 24 static int read_block; 25 static int current_buffer; 26 static int send_id; 27 static int rcv_id; 28 static int max_blocks; 29 static uint32_t bytes_per_block; 30 static uint32_t blocks_submitted; 31 static int is_partial_reconfig; 32 33 struct fpga_config_info { 34 uint32_t addr; 35 int size; 36 int size_written; 37 uint32_t write_requested; 38 int subblocks_sent; 39 int block_number; 40 }; 41 42 /* SiP Service UUID */ 43 DEFINE_SVC_UUID2(intl_svc_uid, 44 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 45 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 46 47 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 48 uint64_t x1, 49 uint64_t x2, 50 uint64_t x3, 51 uint64_t x4, 52 void *cookie, 53 void *handle, 54 uint64_t flags) 55 { 56 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 57 SMC_RET1(handle, SMC_UNK); 58 } 59 60 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 61 62 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 63 { 64 uint32_t args[3]; 65 66 while (max_blocks > 0 && buffer->size > buffer->size_written) { 67 args[0] = (1<<8); 68 args[1] = buffer->addr + buffer->size_written; 69 if (buffer->size - buffer->size_written <= bytes_per_block) { 70 args[2] = buffer->size - buffer->size_written; 71 current_buffer++; 72 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 73 } else 74 args[2] = bytes_per_block; 75 76 buffer->size_written += args[2]; 77 mailbox_send_cmd_async( 78 send_id++ % MBOX_MAX_JOB_ID, 79 MBOX_RECONFIG_DATA, 80 args, 3, 0); 81 82 buffer->subblocks_sent++; 83 max_blocks--; 84 } 85 86 return !max_blocks; 87 } 88 89 static int intel_fpga_sdm_write_all(void) 90 { 91 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 92 if (intel_fpga_sdm_write_buffer( 93 &fpga_config_buffers[current_buffer])) 94 break; 95 return 0; 96 } 97 98 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) 99 { 100 uint32_t ret; 101 102 if (query_type == 1) 103 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); 104 else 105 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); 106 107 if (ret) { 108 if (ret == MBOX_CFGSTAT_STATE_CONFIG) 109 return INTEL_SIP_SMC_STATUS_BUSY; 110 else 111 return INTEL_SIP_SMC_STATUS_ERROR; 112 } 113 114 if (query_type != 1) { 115 /* full reconfiguration */ 116 if (!is_partial_reconfig) 117 socfpga_bridges_enable(); /* Enable bridge */ 118 } 119 120 return INTEL_SIP_SMC_STATUS_OK; 121 } 122 123 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 124 { 125 int i; 126 127 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 128 if (fpga_config_buffers[i].block_number == current_block) { 129 fpga_config_buffers[i].subblocks_sent--; 130 if (fpga_config_buffers[i].subblocks_sent == 0 131 && fpga_config_buffers[i].size <= 132 fpga_config_buffers[i].size_written) { 133 fpga_config_buffers[i].write_requested = 0; 134 current_block++; 135 *buffer_addr_completed = 136 fpga_config_buffers[i].addr; 137 return 0; 138 } 139 } 140 } 141 142 return -1; 143 } 144 145 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 146 uint32_t *count) 147 { 148 uint32_t status = INTEL_SIP_SMC_STATUS_OK; 149 *count = 0; 150 int resp_len = 0; 151 uint32_t resp[5]; 152 int all_completed = 1; 153 154 while (*count < 3) { 155 156 resp_len = mailbox_read_response(rcv_id % MBOX_MAX_JOB_ID, 157 resp, sizeof(resp) / sizeof(resp[0])); 158 159 if (resp_len < 0) 160 break; 161 162 max_blocks++; 163 rcv_id++; 164 165 if (mark_last_buffer_xfer_completed( 166 &completed_addr[*count]) == 0) 167 *count = *count + 1; 168 else 169 break; 170 } 171 172 if (*count <= 0) { 173 if (resp_len != MBOX_NO_RESPONSE && 174 resp_len != MBOX_TIMEOUT && resp_len != 0) { 175 mailbox_clear_response(); 176 return INTEL_SIP_SMC_STATUS_ERROR; 177 } 178 179 *count = 0; 180 } 181 182 intel_fpga_sdm_write_all(); 183 184 if (*count > 0) 185 status = INTEL_SIP_SMC_STATUS_OK; 186 else if (*count == 0) 187 status = INTEL_SIP_SMC_STATUS_BUSY; 188 189 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 190 if (fpga_config_buffers[i].write_requested != 0) { 191 all_completed = 0; 192 break; 193 } 194 } 195 196 if (all_completed == 1) 197 return INTEL_SIP_SMC_STATUS_OK; 198 199 return status; 200 } 201 202 static int intel_fpga_config_start(uint32_t config_type) 203 { 204 uint32_t response[3]; 205 int status = 0; 206 207 is_partial_reconfig = config_type; 208 209 mailbox_clear_response(); 210 211 mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0); 212 213 status = mailbox_send_cmd(1, MBOX_RECONFIG, 0, 0, 0, 214 response, sizeof(response) / sizeof(response[0])); 215 216 if (status < 0) 217 return status; 218 219 max_blocks = response[0]; 220 bytes_per_block = response[1]; 221 222 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 223 fpga_config_buffers[i].size = 0; 224 fpga_config_buffers[i].size_written = 0; 225 fpga_config_buffers[i].addr = 0; 226 fpga_config_buffers[i].write_requested = 0; 227 fpga_config_buffers[i].block_number = 0; 228 fpga_config_buffers[i].subblocks_sent = 0; 229 } 230 231 blocks_submitted = 0; 232 current_block = 0; 233 read_block = 0; 234 current_buffer = 0; 235 send_id = 0; 236 rcv_id = 0; 237 238 /* full reconfiguration */ 239 if (!is_partial_reconfig) { 240 /* Disable bridge */ 241 socfpga_bridges_disable(); 242 } 243 244 return 0; 245 } 246 247 static bool is_fpga_config_buffer_full(void) 248 { 249 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 250 if (!fpga_config_buffers[i].write_requested) 251 return false; 252 return true; 253 } 254 255 static bool is_address_in_ddr_range(uint64_t addr) 256 { 257 if (addr >= DRAM_BASE && addr <= DRAM_BASE + DRAM_SIZE) 258 return true; 259 260 return false; 261 } 262 263 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 264 { 265 int i; 266 267 intel_fpga_sdm_write_all(); 268 269 if (!is_address_in_ddr_range(mem) || 270 !is_address_in_ddr_range(mem + size) || 271 is_fpga_config_buffer_full()) 272 return INTEL_SIP_SMC_STATUS_REJECTED; 273 274 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 275 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 276 277 if (!fpga_config_buffers[j].write_requested) { 278 fpga_config_buffers[j].addr = mem; 279 fpga_config_buffers[j].size = size; 280 fpga_config_buffers[j].size_written = 0; 281 fpga_config_buffers[j].write_requested = 1; 282 fpga_config_buffers[j].block_number = 283 blocks_submitted++; 284 fpga_config_buffers[j].subblocks_sent = 0; 285 break; 286 } 287 } 288 289 if (is_fpga_config_buffer_full()) 290 return INTEL_SIP_SMC_STATUS_BUSY; 291 292 return INTEL_SIP_SMC_STATUS_OK; 293 } 294 295 static int is_out_of_sec_range(uint64_t reg_addr) 296 { 297 switch (reg_addr) { 298 case(0xF8011100): /* ECCCTRL1 */ 299 case(0xF8011104): /* ECCCTRL2 */ 300 case(0xF8011110): /* ERRINTEN */ 301 case(0xF8011114): /* ERRINTENS */ 302 case(0xF8011118): /* ERRINTENR */ 303 case(0xF801111C): /* INTMODE */ 304 case(0xF8011120): /* INTSTAT */ 305 case(0xF8011124): /* DIAGINTTEST */ 306 case(0xF801112C): /* DERRADDRA */ 307 case(0xFFD12028): /* SDMMCGRP_CTRL */ 308 case(0xFFD12044): /* EMAC0 */ 309 case(0xFFD12048): /* EMAC1 */ 310 case(0xFFD1204C): /* EMAC2 */ 311 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 312 case(0xFFD12094): /* ECC_INT_MASK_SET */ 313 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 314 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 315 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 316 case(0xFFD120C0): /* NOC_TIMEOUT */ 317 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 318 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 319 case(0xFFD120D0): /* NOC_IDLEACK */ 320 case(0xFFD120D4): /* NOC_IDLESTATUS */ 321 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 322 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 323 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 324 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 325 return 0; 326 327 default: 328 break; 329 } 330 331 return -1; 332 } 333 334 /* Secure register access */ 335 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 336 { 337 if (is_out_of_sec_range(reg_addr)) 338 return INTEL_SIP_SMC_STATUS_ERROR; 339 340 *retval = mmio_read_32(reg_addr); 341 342 return INTEL_SIP_SMC_STATUS_OK; 343 } 344 345 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 346 uint32_t *retval) 347 { 348 if (is_out_of_sec_range(reg_addr)) 349 return INTEL_SIP_SMC_STATUS_ERROR; 350 351 mmio_write_32(reg_addr, val); 352 353 return intel_secure_reg_read(reg_addr, retval); 354 } 355 356 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 357 uint32_t val, uint32_t *retval) 358 { 359 if (!intel_secure_reg_read(reg_addr, retval)) { 360 *retval &= ~mask; 361 *retval |= val; 362 return intel_secure_reg_write(reg_addr, *retval, retval); 363 } 364 365 return INTEL_SIP_SMC_STATUS_ERROR; 366 } 367 368 /* 369 * This function is responsible for handling all SiP calls from the NS world 370 */ 371 372 uintptr_t sip_smc_handler(uint32_t smc_fid, 373 u_register_t x1, 374 u_register_t x2, 375 u_register_t x3, 376 u_register_t x4, 377 void *cookie, 378 void *handle, 379 u_register_t flags) 380 { 381 uint32_t val = 0; 382 uint32_t status = INTEL_SIP_SMC_STATUS_OK; 383 uint32_t completed_addr[3]; 384 uint32_t count = 0; 385 386 switch (smc_fid) { 387 case SIP_SVC_UID: 388 /* Return UID to the caller */ 389 SMC_UUID_RET(handle, intl_svc_uid); 390 391 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 392 status = intel_mailbox_fpga_config_isdone(x1); 393 SMC_RET4(handle, status, 0, 0, 0); 394 395 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 396 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 397 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 398 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 399 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 400 401 case INTEL_SIP_SMC_FPGA_CONFIG_START: 402 status = intel_fpga_config_start(x1); 403 SMC_RET4(handle, status, 0, 0, 0); 404 405 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 406 status = intel_fpga_config_write(x1, x2); 407 SMC_RET4(handle, status, 0, 0, 0); 408 409 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 410 status = intel_fpga_config_completed_write(completed_addr, 411 &count); 412 switch (count) { 413 case 1: 414 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 415 completed_addr[0], 0, 0); 416 417 case 2: 418 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 419 completed_addr[0], 420 completed_addr[1], 0); 421 422 case 3: 423 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 424 completed_addr[0], 425 completed_addr[1], 426 completed_addr[2]); 427 428 case 0: 429 SMC_RET4(handle, status, 0, 0, 0); 430 431 default: 432 mailbox_clear_response(); 433 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 434 } 435 436 case INTEL_SIP_SMC_REG_READ: 437 status = intel_secure_reg_read(x1, &val); 438 SMC_RET3(handle, status, val, x1); 439 440 case INTEL_SIP_SMC_REG_WRITE: 441 status = intel_secure_reg_write(x1, (uint32_t)x2, &val); 442 SMC_RET3(handle, status, val, x1); 443 444 case INTEL_SIP_SMC_REG_UPDATE: 445 status = intel_secure_reg_update(x1, (uint32_t)x2, 446 (uint32_t)x3, &val); 447 SMC_RET3(handle, status, val, x1); 448 449 default: 450 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 451 cookie, handle, flags); 452 } 453 } 454 455 DECLARE_RT_SVC( 456 socfpga_sip_svc, 457 OEN_SIP_START, 458 OEN_SIP_END, 459 SMC_TYPE_FAST, 460 NULL, 461 sip_smc_handler 462 ); 463 464 DECLARE_RT_SVC( 465 socfpga_sip_svc_std, 466 OEN_SIP_START, 467 OEN_SIP_END, 468 SMC_TYPE_YIELD, 469 NULL, 470 sip_smc_handler 471 ); 472