1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_reset_manager.h" 16 #include "socfpga_sip_svc.h" 17 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static int current_block, current_buffer; 23 static int read_block, max_blocks; 24 static uint32_t send_id, rcv_id; 25 static uint32_t bytes_per_block, blocks_submitted; 26 static bool bridge_disable; 27 28 /* RSU static variables */ 29 static uint32_t rsu_dcmf_ver[4] = {0}; 30 31 /* RSU Max Retry */ 32 static uint32_t rsu_max_retry; 33 static uint16_t rsu_dcmf_stat[4] = {0}; 34 35 /* SiP Service UUID */ 36 DEFINE_SVC_UUID2(intl_svc_uid, 37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 39 40 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 41 uint64_t x1, 42 uint64_t x2, 43 uint64_t x3, 44 uint64_t x4, 45 void *cookie, 46 void *handle, 47 uint64_t flags) 48 { 49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 50 SMC_RET1(handle, SMC_UNK); 51 } 52 53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 54 55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 56 { 57 uint32_t args[3]; 58 59 while (max_blocks > 0 && buffer->size > buffer->size_written) { 60 args[0] = (1<<8); 61 args[1] = buffer->addr + buffer->size_written; 62 if (buffer->size - buffer->size_written <= bytes_per_block) { 63 args[2] = buffer->size - buffer->size_written; 64 current_buffer++; 65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 66 } else 67 args[2] = bytes_per_block; 68 69 buffer->size_written += args[2]; 70 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 71 3U, CMD_INDIRECT); 72 73 buffer->subblocks_sent++; 74 max_blocks--; 75 } 76 77 return !max_blocks; 78 } 79 80 static int intel_fpga_sdm_write_all(void) 81 { 82 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 83 if (intel_fpga_sdm_write_buffer( 84 &fpga_config_buffers[current_buffer])) 85 break; 86 return 0; 87 } 88 89 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) 90 { 91 uint32_t ret; 92 93 if (query_type == 1U) { 94 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false); 95 } else { 96 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); 97 } 98 99 if (ret != 0U) { 100 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 101 return INTEL_SIP_SMC_STATUS_BUSY; 102 } else { 103 return INTEL_SIP_SMC_STATUS_ERROR; 104 } 105 } 106 107 if (bridge_disable) { 108 socfpga_bridges_enable(~0); /* Enable bridge */ 109 bridge_disable = false; 110 } 111 112 return INTEL_SIP_SMC_STATUS_OK; 113 } 114 115 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 116 { 117 int i; 118 119 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 120 if (fpga_config_buffers[i].block_number == current_block) { 121 fpga_config_buffers[i].subblocks_sent--; 122 if (fpga_config_buffers[i].subblocks_sent == 0 123 && fpga_config_buffers[i].size <= 124 fpga_config_buffers[i].size_written) { 125 fpga_config_buffers[i].write_requested = 0; 126 current_block++; 127 *buffer_addr_completed = 128 fpga_config_buffers[i].addr; 129 return 0; 130 } 131 } 132 } 133 134 return -1; 135 } 136 137 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 138 uint32_t *count, uint32_t *job_id) 139 { 140 uint32_t resp[5]; 141 unsigned int resp_len = ARRAY_SIZE(resp); 142 int status = INTEL_SIP_SMC_STATUS_OK; 143 int all_completed = 1; 144 *count = 0; 145 146 while (*count < 3) { 147 148 status = mailbox_read_response(job_id, 149 resp, &resp_len); 150 151 if (status < 0) { 152 break; 153 } 154 155 max_blocks++; 156 157 if (mark_last_buffer_xfer_completed( 158 &completed_addr[*count]) == 0) { 159 *count = *count + 1; 160 } else { 161 break; 162 } 163 } 164 165 if (*count <= 0) { 166 if (status != MBOX_NO_RESPONSE && 167 status != MBOX_TIMEOUT && resp_len != 0) { 168 mailbox_clear_response(); 169 return INTEL_SIP_SMC_STATUS_ERROR; 170 } 171 172 *count = 0; 173 } 174 175 intel_fpga_sdm_write_all(); 176 177 if (*count > 0) 178 status = INTEL_SIP_SMC_STATUS_OK; 179 else if (*count == 0) 180 status = INTEL_SIP_SMC_STATUS_BUSY; 181 182 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 183 if (fpga_config_buffers[i].write_requested != 0) { 184 all_completed = 0; 185 break; 186 } 187 } 188 189 if (all_completed == 1) 190 return INTEL_SIP_SMC_STATUS_OK; 191 192 return status; 193 } 194 195 static int intel_fpga_config_start(uint32_t flag) 196 { 197 uint32_t argument = 0x1; 198 uint32_t response[3]; 199 int status = 0; 200 unsigned int size = 0; 201 unsigned int resp_len = ARRAY_SIZE(response); 202 203 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 204 bridge_disable = true; 205 } 206 207 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 208 size = 1; 209 bridge_disable = false; 210 } 211 212 mailbox_clear_response(); 213 214 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 215 CMD_CASUAL, NULL, NULL); 216 217 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 218 CMD_CASUAL, response, &resp_len); 219 220 if (status < 0) { 221 bridge_disable = false; 222 return INTEL_SIP_SMC_STATUS_ERROR; 223 } 224 225 max_blocks = response[0]; 226 bytes_per_block = response[1]; 227 228 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 229 fpga_config_buffers[i].size = 0; 230 fpga_config_buffers[i].size_written = 0; 231 fpga_config_buffers[i].addr = 0; 232 fpga_config_buffers[i].write_requested = 0; 233 fpga_config_buffers[i].block_number = 0; 234 fpga_config_buffers[i].subblocks_sent = 0; 235 } 236 237 blocks_submitted = 0; 238 current_block = 0; 239 read_block = 0; 240 current_buffer = 0; 241 242 /* Disable bridge on full reconfiguration */ 243 if (bridge_disable) { 244 socfpga_bridges_disable(~0); 245 } 246 247 return INTEL_SIP_SMC_STATUS_OK; 248 } 249 250 static bool is_fpga_config_buffer_full(void) 251 { 252 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 253 if (!fpga_config_buffers[i].write_requested) 254 return false; 255 return true; 256 } 257 258 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 259 { 260 if (!addr && !size) { 261 return true; 262 } 263 if (size > (UINT64_MAX - addr)) 264 return false; 265 if (addr < BL31_LIMIT) 266 return false; 267 if (addr + size > DRAM_BASE + DRAM_SIZE) 268 return false; 269 270 return true; 271 } 272 273 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 274 { 275 int i; 276 277 intel_fpga_sdm_write_all(); 278 279 if (!is_address_in_ddr_range(mem, size) || 280 is_fpga_config_buffer_full()) { 281 return INTEL_SIP_SMC_STATUS_REJECTED; 282 } 283 284 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 285 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 286 287 if (!fpga_config_buffers[j].write_requested) { 288 fpga_config_buffers[j].addr = mem; 289 fpga_config_buffers[j].size = size; 290 fpga_config_buffers[j].size_written = 0; 291 fpga_config_buffers[j].write_requested = 1; 292 fpga_config_buffers[j].block_number = 293 blocks_submitted++; 294 fpga_config_buffers[j].subblocks_sent = 0; 295 break; 296 } 297 } 298 299 if (is_fpga_config_buffer_full()) { 300 return INTEL_SIP_SMC_STATUS_BUSY; 301 } 302 303 return INTEL_SIP_SMC_STATUS_OK; 304 } 305 306 static int is_out_of_sec_range(uint64_t reg_addr) 307 { 308 #if DEBUG 309 return 0; 310 #endif 311 312 switch (reg_addr) { 313 case(0xF8011100): /* ECCCTRL1 */ 314 case(0xF8011104): /* ECCCTRL2 */ 315 case(0xF8011110): /* ERRINTEN */ 316 case(0xF8011114): /* ERRINTENS */ 317 case(0xF8011118): /* ERRINTENR */ 318 case(0xF801111C): /* INTMODE */ 319 case(0xF8011120): /* INTSTAT */ 320 case(0xF8011124): /* DIAGINTTEST */ 321 case(0xF801112C): /* DERRADDRA */ 322 case(0xFFD12028): /* SDMMCGRP_CTRL */ 323 case(0xFFD12044): /* EMAC0 */ 324 case(0xFFD12048): /* EMAC1 */ 325 case(0xFFD1204C): /* EMAC2 */ 326 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 327 case(0xFFD12094): /* ECC_INT_MASK_SET */ 328 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 329 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 330 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 331 case(0xFFD120C0): /* NOC_TIMEOUT */ 332 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 333 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 334 case(0xFFD120D0): /* NOC_IDLEACK */ 335 case(0xFFD120D4): /* NOC_IDLESTATUS */ 336 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 337 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 338 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 339 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 340 return 0; 341 342 default: 343 break; 344 } 345 346 return -1; 347 } 348 349 /* Secure register access */ 350 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 351 { 352 if (is_out_of_sec_range(reg_addr)) 353 return INTEL_SIP_SMC_STATUS_ERROR; 354 355 *retval = mmio_read_32(reg_addr); 356 357 return INTEL_SIP_SMC_STATUS_OK; 358 } 359 360 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 361 uint32_t *retval) 362 { 363 if (is_out_of_sec_range(reg_addr)) 364 return INTEL_SIP_SMC_STATUS_ERROR; 365 366 mmio_write_32(reg_addr, val); 367 368 return intel_secure_reg_read(reg_addr, retval); 369 } 370 371 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 372 uint32_t val, uint32_t *retval) 373 { 374 if (!intel_secure_reg_read(reg_addr, retval)) { 375 *retval &= ~mask; 376 *retval |= val & mask; 377 return intel_secure_reg_write(reg_addr, *retval, retval); 378 } 379 380 return INTEL_SIP_SMC_STATUS_ERROR; 381 } 382 383 /* Intel Remote System Update (RSU) services */ 384 uint64_t intel_rsu_update_address; 385 386 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 387 { 388 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 389 return INTEL_SIP_SMC_RSU_ERROR; 390 391 return INTEL_SIP_SMC_STATUS_OK; 392 } 393 394 static uint32_t intel_rsu_update(uint64_t update_address) 395 { 396 intel_rsu_update_address = update_address; 397 return INTEL_SIP_SMC_STATUS_OK; 398 } 399 400 static uint32_t intel_rsu_notify(uint32_t execution_stage) 401 { 402 if (mailbox_hps_stage_notify(execution_stage) < 0) 403 return INTEL_SIP_SMC_RSU_ERROR; 404 405 return INTEL_SIP_SMC_STATUS_OK; 406 } 407 408 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 409 uint32_t *ret_stat) 410 { 411 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 412 return INTEL_SIP_SMC_RSU_ERROR; 413 414 *ret_stat = respbuf[8]; 415 return INTEL_SIP_SMC_STATUS_OK; 416 } 417 418 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 419 uint64_t dcmf_ver_3_2) 420 { 421 rsu_dcmf_ver[0] = dcmf_ver_1_0; 422 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 423 rsu_dcmf_ver[2] = dcmf_ver_3_2; 424 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 425 426 return INTEL_SIP_SMC_STATUS_OK; 427 } 428 429 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 430 { 431 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 432 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 433 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 434 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 435 436 return INTEL_SIP_SMC_STATUS_OK; 437 } 438 439 /* Intel HWMON services */ 440 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 441 { 442 if (chan > TEMP_CHANNEL_MAX) { 443 return INTEL_SIP_SMC_STATUS_ERROR; 444 } 445 446 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 447 return INTEL_SIP_SMC_STATUS_ERROR; 448 } 449 450 return INTEL_SIP_SMC_STATUS_OK; 451 } 452 453 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 454 { 455 if (chan > VOLT_CHANNEL_MAX) { 456 return INTEL_SIP_SMC_STATUS_ERROR; 457 } 458 459 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 460 return INTEL_SIP_SMC_STATUS_ERROR; 461 } 462 463 return INTEL_SIP_SMC_STATUS_OK; 464 } 465 466 /* Mailbox services */ 467 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 468 { 469 int status; 470 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 471 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 472 473 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 474 CMD_CASUAL, resp_data, &resp_len); 475 476 if (status < 0) { 477 return INTEL_SIP_SMC_STATUS_ERROR; 478 } 479 480 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 481 return INTEL_SIP_SMC_STATUS_ERROR; 482 } 483 484 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 485 486 return INTEL_SIP_SMC_STATUS_OK; 487 } 488 489 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 490 unsigned int len, 491 uint32_t urgent, uint32_t *response, 492 unsigned int resp_len, int *mbox_status, 493 unsigned int *len_in_resp) 494 { 495 *len_in_resp = 0; 496 *mbox_status = GENERIC_RESPONSE_ERROR; 497 498 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) 499 return INTEL_SIP_SMC_STATUS_REJECTED; 500 501 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 502 response, &resp_len); 503 504 if (status < 0) { 505 *mbox_status = -status; 506 return INTEL_SIP_SMC_STATUS_ERROR; 507 } 508 509 *mbox_status = 0; 510 *len_in_resp = resp_len; 511 return INTEL_SIP_SMC_STATUS_OK; 512 } 513 514 static int intel_smc_get_usercode(uint32_t *user_code) 515 { 516 int status; 517 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 518 519 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 520 0U, CMD_CASUAL, user_code, &resp_len); 521 522 if (status < 0) { 523 return INTEL_SIP_SMC_STATUS_ERROR; 524 } 525 526 return INTEL_SIP_SMC_STATUS_OK; 527 } 528 529 /* Miscellaneous HPS services */ 530 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 531 { 532 int status = 0; 533 534 if (enable & SOCFPGA_BRIDGE_ENABLE) { 535 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0) { 536 status = socfpga_bridges_enable((uint32_t)mask); 537 } else { 538 status = socfpga_bridges_enable(~0); 539 } 540 } else { 541 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0) { 542 status = socfpga_bridges_disable((uint32_t)mask); 543 } else { 544 status = socfpga_bridges_disable(~0); 545 } 546 } 547 548 if (status < 0) { 549 return INTEL_SIP_SMC_STATUS_ERROR; 550 } 551 552 return INTEL_SIP_SMC_STATUS_OK; 553 } 554 555 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 556 uint32_t mode, uint32_t *job_id, 557 uint32_t *ret_size, uint32_t *mbox_error) 558 { 559 int status = 0; 560 uint32_t resp_len = size / MBOX_WORD_BYTE; 561 562 if (resp_len > MBOX_DATA_MAX_LEN) { 563 return INTEL_SIP_SMC_STATUS_REJECTED; 564 } 565 566 if (!is_address_in_ddr_range(addr, size)) { 567 return INTEL_SIP_SMC_STATUS_REJECTED; 568 } 569 570 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 571 status = mailbox_read_response_async(job_id, 572 NULL, (uint32_t *) addr, &resp_len, 0); 573 } else { 574 status = mailbox_read_response(job_id, 575 (uint32_t *) addr, &resp_len); 576 577 if (status == MBOX_NO_RESPONSE) { 578 status = MBOX_BUSY; 579 } 580 } 581 582 if (status == MBOX_NO_RESPONSE) { 583 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 584 } 585 586 if (status == MBOX_BUSY) { 587 return INTEL_SIP_SMC_STATUS_BUSY; 588 } 589 590 *ret_size = resp_len * MBOX_WORD_BYTE; 591 flush_dcache_range(addr, *ret_size); 592 593 if (status != MBOX_RET_OK) { 594 *mbox_error = -status; 595 return INTEL_SIP_SMC_STATUS_ERROR; 596 } 597 598 return INTEL_SIP_SMC_STATUS_OK; 599 } 600 601 /* 602 * This function is responsible for handling all SiP calls from the NS world 603 */ 604 605 uintptr_t sip_smc_handler(uint32_t smc_fid, 606 u_register_t x1, 607 u_register_t x2, 608 u_register_t x3, 609 u_register_t x4, 610 void *cookie, 611 void *handle, 612 u_register_t flags) 613 { 614 uint32_t retval = 0, completed_addr[3]; 615 uint32_t retval2 = 0; 616 uint32_t mbox_error = 0; 617 uint64_t retval64, rsu_respbuf[9]; 618 int status = INTEL_SIP_SMC_STATUS_OK; 619 int mbox_status; 620 unsigned int len_in_resp; 621 u_register_t x5, x6; 622 623 switch (smc_fid) { 624 case SIP_SVC_UID: 625 /* Return UID to the caller */ 626 SMC_UUID_RET(handle, intl_svc_uid); 627 628 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 629 status = intel_mailbox_fpga_config_isdone(x1); 630 SMC_RET4(handle, status, 0, 0, 0); 631 632 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 633 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 634 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 635 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 636 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 637 638 case INTEL_SIP_SMC_FPGA_CONFIG_START: 639 status = intel_fpga_config_start(x1); 640 SMC_RET4(handle, status, 0, 0, 0); 641 642 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 643 status = intel_fpga_config_write(x1, x2); 644 SMC_RET4(handle, status, 0, 0, 0); 645 646 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 647 status = intel_fpga_config_completed_write(completed_addr, 648 &retval, &rcv_id); 649 switch (retval) { 650 case 1: 651 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 652 completed_addr[0], 0, 0); 653 654 case 2: 655 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 656 completed_addr[0], 657 completed_addr[1], 0); 658 659 case 3: 660 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 661 completed_addr[0], 662 completed_addr[1], 663 completed_addr[2]); 664 665 case 0: 666 SMC_RET4(handle, status, 0, 0, 0); 667 668 default: 669 mailbox_clear_response(); 670 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 671 } 672 673 case INTEL_SIP_SMC_REG_READ: 674 status = intel_secure_reg_read(x1, &retval); 675 SMC_RET3(handle, status, retval, x1); 676 677 case INTEL_SIP_SMC_REG_WRITE: 678 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 679 SMC_RET3(handle, status, retval, x1); 680 681 case INTEL_SIP_SMC_REG_UPDATE: 682 status = intel_secure_reg_update(x1, (uint32_t)x2, 683 (uint32_t)x3, &retval); 684 SMC_RET3(handle, status, retval, x1); 685 686 case INTEL_SIP_SMC_RSU_STATUS: 687 status = intel_rsu_status(rsu_respbuf, 688 ARRAY_SIZE(rsu_respbuf)); 689 if (status) { 690 SMC_RET1(handle, status); 691 } else { 692 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 693 rsu_respbuf[2], rsu_respbuf[3]); 694 } 695 696 case INTEL_SIP_SMC_RSU_UPDATE: 697 status = intel_rsu_update(x1); 698 SMC_RET1(handle, status); 699 700 case INTEL_SIP_SMC_RSU_NOTIFY: 701 status = intel_rsu_notify(x1); 702 SMC_RET1(handle, status); 703 704 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 705 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 706 ARRAY_SIZE(rsu_respbuf), &retval); 707 if (status) { 708 SMC_RET1(handle, status); 709 } else { 710 SMC_RET2(handle, status, retval); 711 } 712 713 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 714 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 715 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 716 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 717 718 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 719 status = intel_rsu_copy_dcmf_version(x1, x2); 720 SMC_RET1(handle, status); 721 722 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 723 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 724 ((uint64_t)rsu_dcmf_stat[3] << 48) | 725 ((uint64_t)rsu_dcmf_stat[2] << 32) | 726 ((uint64_t)rsu_dcmf_stat[1] << 16) | 727 rsu_dcmf_stat[0]); 728 729 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 730 status = intel_rsu_copy_dcmf_status(x1); 731 SMC_RET1(handle, status); 732 733 case INTEL_SIP_SMC_RSU_MAX_RETRY: 734 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 735 736 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 737 rsu_max_retry = x1; 738 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 739 740 case INTEL_SIP_SMC_ECC_DBE: 741 status = intel_ecc_dbe_notification(x1); 742 SMC_RET1(handle, status); 743 744 case INTEL_SIP_SMC_FIRMWARE_VERSION: 745 status = intel_smc_fw_version(&retval); 746 SMC_RET2(handle, status, retval); 747 748 case INTEL_SIP_SMC_MBOX_SEND_CMD: 749 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 750 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 751 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, 752 (uint32_t *)x5, x6, &mbox_status, 753 &len_in_resp); 754 SMC_RET3(handle, status, mbox_status, len_in_resp); 755 756 case INTEL_SIP_SMC_GET_USERCODE: 757 status = intel_smc_get_usercode(&retval); 758 SMC_RET2(handle, status, retval); 759 760 case INTEL_SIP_SMC_FCS_CRYPTION: 761 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 762 763 if (x1 == FCS_MODE_DECRYPT) { 764 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 765 } else if (x1 == FCS_MODE_ENCRYPT) { 766 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 767 } else { 768 status = INTEL_SIP_SMC_STATUS_REJECTED; 769 } 770 771 SMC_RET3(handle, status, x4, x5); 772 773 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 774 status = intel_fcs_random_number_gen(x1, &retval64, 775 &mbox_error); 776 SMC_RET4(handle, status, mbox_error, x1, retval64); 777 778 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 779 status = intel_fcs_send_cert(x1, x2, &send_id); 780 SMC_RET1(handle, status); 781 782 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 783 status = intel_fcs_get_provision_data(&send_id); 784 SMC_RET1(handle, status); 785 786 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 787 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 788 &mbox_error); 789 SMC_RET2(handle, status, mbox_error); 790 791 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 792 status = intel_hps_set_bridges(x1, x2); 793 SMC_RET1(handle, status); 794 795 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 796 status = intel_fcs_sigma_teardown(x1, &mbox_error); 797 SMC_RET2(handle, status, mbox_error); 798 799 case INTEL_SIP_SMC_FCS_CHIP_ID: 800 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 801 SMC_RET4(handle, status, mbox_error, retval, retval2); 802 803 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 804 status = intel_fcs_attestation_subkey(x1, x2, x3, 805 (uint32_t *) &x4, &mbox_error); 806 SMC_RET4(handle, status, mbox_error, x3, x4); 807 808 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 809 status = intel_fcs_get_measurement(x1, x2, x3, 810 (uint32_t *) &x4, &mbox_error); 811 SMC_RET4(handle, status, mbox_error, x3, x4); 812 813 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 814 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 815 &mbox_error); 816 SMC_RET4(handle, status, mbox_error, x1, retval64); 817 818 case INTEL_SIP_SMC_SVC_VERSION: 819 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 820 SIP_SVC_VERSION_MAJOR, 821 SIP_SVC_VERSION_MINOR); 822 823 case INTEL_SIP_SMC_HWMON_READTEMP: 824 status = intel_hwmon_readtemp(x1, &retval); 825 SMC_RET2(handle, status, retval); 826 827 case INTEL_SIP_SMC_HWMON_READVOLT: 828 status = intel_hwmon_readvolt(x1, &retval); 829 SMC_RET2(handle, status, retval); 830 831 default: 832 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 833 cookie, handle, flags); 834 } 835 } 836 837 DECLARE_RT_SVC( 838 socfpga_sip_svc, 839 OEN_SIP_START, 840 OEN_SIP_END, 841 SMC_TYPE_FAST, 842 NULL, 843 sip_smc_handler 844 ); 845 846 DECLARE_RT_SVC( 847 socfpga_sip_svc_std, 848 OEN_SIP_START, 849 OEN_SIP_END, 850 SMC_TYPE_YIELD, 851 NULL, 852 sip_smc_handler 853 ); 854