1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_reset_manager.h" 16 #include "socfpga_sip_svc.h" 17 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static int current_block, current_buffer; 23 static int read_block, max_blocks; 24 static uint32_t send_id, rcv_id; 25 static uint32_t bytes_per_block, blocks_submitted; 26 static bool bridge_disable; 27 28 /* RSU static variables */ 29 static uint32_t rsu_dcmf_ver[4] = {0}; 30 31 /* RSU Max Retry */ 32 static uint32_t rsu_max_retry; 33 static uint16_t rsu_dcmf_stat[4] = {0}; 34 35 /* SiP Service UUID */ 36 DEFINE_SVC_UUID2(intl_svc_uid, 37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 39 40 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 41 uint64_t x1, 42 uint64_t x2, 43 uint64_t x3, 44 uint64_t x4, 45 void *cookie, 46 void *handle, 47 uint64_t flags) 48 { 49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 50 SMC_RET1(handle, SMC_UNK); 51 } 52 53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 54 55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 56 { 57 uint32_t args[3]; 58 59 while (max_blocks > 0 && buffer->size > buffer->size_written) { 60 args[0] = (1<<8); 61 args[1] = buffer->addr + buffer->size_written; 62 if (buffer->size - buffer->size_written <= bytes_per_block) { 63 args[2] = buffer->size - buffer->size_written; 64 current_buffer++; 65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 66 } else { 67 args[2] = bytes_per_block; 68 } 69 70 buffer->size_written += args[2]; 71 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 72 3U, CMD_INDIRECT); 73 74 buffer->subblocks_sent++; 75 max_blocks--; 76 } 77 78 return !max_blocks; 79 } 80 81 static int intel_fpga_sdm_write_all(void) 82 { 83 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 84 if (intel_fpga_sdm_write_buffer( 85 &fpga_config_buffers[current_buffer])) { 86 break; 87 } 88 } 89 return 0; 90 } 91 92 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) 93 { 94 uint32_t ret; 95 96 if (query_type == 1U) { 97 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false); 98 } else { 99 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); 100 } 101 102 if (ret != 0U) { 103 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 104 return INTEL_SIP_SMC_STATUS_BUSY; 105 } else { 106 return INTEL_SIP_SMC_STATUS_ERROR; 107 } 108 } 109 110 if (bridge_disable) { 111 socfpga_bridges_enable(~0); /* Enable bridge */ 112 bridge_disable = false; 113 } 114 115 return INTEL_SIP_SMC_STATUS_OK; 116 } 117 118 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 119 { 120 int i; 121 122 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 123 if (fpga_config_buffers[i].block_number == current_block) { 124 fpga_config_buffers[i].subblocks_sent--; 125 if (fpga_config_buffers[i].subblocks_sent == 0 126 && fpga_config_buffers[i].size <= 127 fpga_config_buffers[i].size_written) { 128 fpga_config_buffers[i].write_requested = 0; 129 current_block++; 130 *buffer_addr_completed = 131 fpga_config_buffers[i].addr; 132 return 0; 133 } 134 } 135 } 136 137 return -1; 138 } 139 140 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 141 uint32_t *count, uint32_t *job_id) 142 { 143 uint32_t resp[5]; 144 unsigned int resp_len = ARRAY_SIZE(resp); 145 int status = INTEL_SIP_SMC_STATUS_OK; 146 int all_completed = 1; 147 *count = 0; 148 149 while (*count < 3) { 150 151 status = mailbox_read_response(job_id, 152 resp, &resp_len); 153 154 if (status < 0) { 155 break; 156 } 157 158 max_blocks++; 159 160 if (mark_last_buffer_xfer_completed( 161 &completed_addr[*count]) == 0) { 162 *count = *count + 1; 163 } else { 164 break; 165 } 166 } 167 168 if (*count <= 0) { 169 if (status != MBOX_NO_RESPONSE && 170 status != MBOX_TIMEOUT && resp_len != 0) { 171 mailbox_clear_response(); 172 return INTEL_SIP_SMC_STATUS_ERROR; 173 } 174 175 *count = 0; 176 } 177 178 intel_fpga_sdm_write_all(); 179 180 if (*count > 0) { 181 status = INTEL_SIP_SMC_STATUS_OK; 182 } else if (*count == 0) { 183 status = INTEL_SIP_SMC_STATUS_BUSY; 184 } 185 186 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 187 if (fpga_config_buffers[i].write_requested != 0) { 188 all_completed = 0; 189 break; 190 } 191 } 192 193 if (all_completed == 1) { 194 return INTEL_SIP_SMC_STATUS_OK; 195 } 196 197 return status; 198 } 199 200 static int intel_fpga_config_start(uint32_t flag) 201 { 202 uint32_t argument = 0x1; 203 uint32_t response[3]; 204 int status = 0; 205 unsigned int size = 0; 206 unsigned int resp_len = ARRAY_SIZE(response); 207 208 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 209 bridge_disable = true; 210 } 211 212 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 213 size = 1; 214 bridge_disable = false; 215 } 216 217 mailbox_clear_response(); 218 219 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 220 CMD_CASUAL, NULL, NULL); 221 222 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 223 CMD_CASUAL, response, &resp_len); 224 225 if (status < 0) { 226 bridge_disable = false; 227 return INTEL_SIP_SMC_STATUS_ERROR; 228 } 229 230 max_blocks = response[0]; 231 bytes_per_block = response[1]; 232 233 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 234 fpga_config_buffers[i].size = 0; 235 fpga_config_buffers[i].size_written = 0; 236 fpga_config_buffers[i].addr = 0; 237 fpga_config_buffers[i].write_requested = 0; 238 fpga_config_buffers[i].block_number = 0; 239 fpga_config_buffers[i].subblocks_sent = 0; 240 } 241 242 blocks_submitted = 0; 243 current_block = 0; 244 read_block = 0; 245 current_buffer = 0; 246 247 /* Disable bridge on full reconfiguration */ 248 if (bridge_disable) { 249 socfpga_bridges_disable(~0); 250 } 251 252 return INTEL_SIP_SMC_STATUS_OK; 253 } 254 255 static bool is_fpga_config_buffer_full(void) 256 { 257 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 258 if (!fpga_config_buffers[i].write_requested) { 259 return false; 260 } 261 } 262 return true; 263 } 264 265 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 266 { 267 if (!addr && !size) { 268 return true; 269 } 270 if (size > (UINT64_MAX - addr)) { 271 return false; 272 } 273 if (addr < BL31_LIMIT) { 274 return false; 275 } 276 if (addr + size > DRAM_BASE + DRAM_SIZE) { 277 return false; 278 } 279 280 return true; 281 } 282 283 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 284 { 285 int i; 286 287 intel_fpga_sdm_write_all(); 288 289 if (!is_address_in_ddr_range(mem, size) || 290 is_fpga_config_buffer_full()) { 291 return INTEL_SIP_SMC_STATUS_REJECTED; 292 } 293 294 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 295 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 296 297 if (!fpga_config_buffers[j].write_requested) { 298 fpga_config_buffers[j].addr = mem; 299 fpga_config_buffers[j].size = size; 300 fpga_config_buffers[j].size_written = 0; 301 fpga_config_buffers[j].write_requested = 1; 302 fpga_config_buffers[j].block_number = 303 blocks_submitted++; 304 fpga_config_buffers[j].subblocks_sent = 0; 305 break; 306 } 307 } 308 309 if (is_fpga_config_buffer_full()) { 310 return INTEL_SIP_SMC_STATUS_BUSY; 311 } 312 313 return INTEL_SIP_SMC_STATUS_OK; 314 } 315 316 static int is_out_of_sec_range(uint64_t reg_addr) 317 { 318 #if DEBUG 319 return 0; 320 #endif 321 322 switch (reg_addr) { 323 case(0xF8011100): /* ECCCTRL1 */ 324 case(0xF8011104): /* ECCCTRL2 */ 325 case(0xF8011110): /* ERRINTEN */ 326 case(0xF8011114): /* ERRINTENS */ 327 case(0xF8011118): /* ERRINTENR */ 328 case(0xF801111C): /* INTMODE */ 329 case(0xF8011120): /* INTSTAT */ 330 case(0xF8011124): /* DIAGINTTEST */ 331 case(0xF801112C): /* DERRADDRA */ 332 case(0xFFD12028): /* SDMMCGRP_CTRL */ 333 case(0xFFD12044): /* EMAC0 */ 334 case(0xFFD12048): /* EMAC1 */ 335 case(0xFFD1204C): /* EMAC2 */ 336 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 337 case(0xFFD12094): /* ECC_INT_MASK_SET */ 338 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 339 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 340 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 341 case(0xFFD120C0): /* NOC_TIMEOUT */ 342 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 343 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 344 case(0xFFD120D0): /* NOC_IDLEACK */ 345 case(0xFFD120D4): /* NOC_IDLESTATUS */ 346 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 347 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 348 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 349 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 350 return 0; 351 352 default: 353 break; 354 } 355 356 return -1; 357 } 358 359 /* Secure register access */ 360 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 361 { 362 if (is_out_of_sec_range(reg_addr)) { 363 return INTEL_SIP_SMC_STATUS_ERROR; 364 } 365 366 *retval = mmio_read_32(reg_addr); 367 368 return INTEL_SIP_SMC_STATUS_OK; 369 } 370 371 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 372 uint32_t *retval) 373 { 374 if (is_out_of_sec_range(reg_addr)) { 375 return INTEL_SIP_SMC_STATUS_ERROR; 376 } 377 378 mmio_write_32(reg_addr, val); 379 380 return intel_secure_reg_read(reg_addr, retval); 381 } 382 383 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 384 uint32_t val, uint32_t *retval) 385 { 386 if (!intel_secure_reg_read(reg_addr, retval)) { 387 *retval &= ~mask; 388 *retval |= val & mask; 389 return intel_secure_reg_write(reg_addr, *retval, retval); 390 } 391 392 return INTEL_SIP_SMC_STATUS_ERROR; 393 } 394 395 /* Intel Remote System Update (RSU) services */ 396 uint64_t intel_rsu_update_address; 397 398 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 399 { 400 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 401 return INTEL_SIP_SMC_RSU_ERROR; 402 } 403 404 return INTEL_SIP_SMC_STATUS_OK; 405 } 406 407 static uint32_t intel_rsu_update(uint64_t update_address) 408 { 409 intel_rsu_update_address = update_address; 410 return INTEL_SIP_SMC_STATUS_OK; 411 } 412 413 static uint32_t intel_rsu_notify(uint32_t execution_stage) 414 { 415 if (mailbox_hps_stage_notify(execution_stage) < 0) { 416 return INTEL_SIP_SMC_RSU_ERROR; 417 } 418 419 return INTEL_SIP_SMC_STATUS_OK; 420 } 421 422 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 423 uint32_t *ret_stat) 424 { 425 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 426 return INTEL_SIP_SMC_RSU_ERROR; 427 } 428 429 *ret_stat = respbuf[8]; 430 return INTEL_SIP_SMC_STATUS_OK; 431 } 432 433 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 434 uint64_t dcmf_ver_3_2) 435 { 436 rsu_dcmf_ver[0] = dcmf_ver_1_0; 437 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 438 rsu_dcmf_ver[2] = dcmf_ver_3_2; 439 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 440 441 return INTEL_SIP_SMC_STATUS_OK; 442 } 443 444 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 445 { 446 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 447 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 448 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 449 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 450 451 return INTEL_SIP_SMC_STATUS_OK; 452 } 453 454 /* Intel HWMON services */ 455 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 456 { 457 if (chan > TEMP_CHANNEL_MAX) { 458 return INTEL_SIP_SMC_STATUS_ERROR; 459 } 460 461 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 462 return INTEL_SIP_SMC_STATUS_ERROR; 463 } 464 465 return INTEL_SIP_SMC_STATUS_OK; 466 } 467 468 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 469 { 470 if (chan > VOLT_CHANNEL_MAX) { 471 return INTEL_SIP_SMC_STATUS_ERROR; 472 } 473 474 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 475 return INTEL_SIP_SMC_STATUS_ERROR; 476 } 477 478 return INTEL_SIP_SMC_STATUS_OK; 479 } 480 481 /* Mailbox services */ 482 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 483 { 484 int status; 485 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 486 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 487 488 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 489 CMD_CASUAL, resp_data, &resp_len); 490 491 if (status < 0) { 492 return INTEL_SIP_SMC_STATUS_ERROR; 493 } 494 495 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 496 return INTEL_SIP_SMC_STATUS_ERROR; 497 } 498 499 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 500 501 return INTEL_SIP_SMC_STATUS_OK; 502 } 503 504 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 505 unsigned int len, 506 uint32_t urgent, uint32_t *response, 507 unsigned int resp_len, int *mbox_status, 508 unsigned int *len_in_resp) 509 { 510 *len_in_resp = 0; 511 *mbox_status = GENERIC_RESPONSE_ERROR; 512 513 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 514 return INTEL_SIP_SMC_STATUS_REJECTED; 515 } 516 517 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 518 response, &resp_len); 519 520 if (status < 0) { 521 *mbox_status = -status; 522 return INTEL_SIP_SMC_STATUS_ERROR; 523 } 524 525 *mbox_status = 0; 526 *len_in_resp = resp_len; 527 return INTEL_SIP_SMC_STATUS_OK; 528 } 529 530 static int intel_smc_get_usercode(uint32_t *user_code) 531 { 532 int status; 533 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 534 535 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 536 0U, CMD_CASUAL, user_code, &resp_len); 537 538 if (status < 0) { 539 return INTEL_SIP_SMC_STATUS_ERROR; 540 } 541 542 return INTEL_SIP_SMC_STATUS_OK; 543 } 544 545 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 546 uint32_t mode, uint32_t *job_id, 547 uint32_t *ret_size, uint32_t *mbox_error) 548 { 549 int status = 0; 550 uint32_t resp_len = size / MBOX_WORD_BYTE; 551 552 if (resp_len > MBOX_DATA_MAX_LEN) { 553 return INTEL_SIP_SMC_STATUS_REJECTED; 554 } 555 556 if (!is_address_in_ddr_range(addr, size)) { 557 return INTEL_SIP_SMC_STATUS_REJECTED; 558 } 559 560 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 561 status = mailbox_read_response_async(job_id, 562 NULL, (uint32_t *) addr, &resp_len, 0); 563 } else { 564 status = mailbox_read_response(job_id, 565 (uint32_t *) addr, &resp_len); 566 567 if (status == MBOX_NO_RESPONSE) { 568 status = MBOX_BUSY; 569 } 570 } 571 572 if (status == MBOX_NO_RESPONSE) { 573 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 574 } 575 576 if (status == MBOX_BUSY) { 577 return INTEL_SIP_SMC_STATUS_BUSY; 578 } 579 580 *ret_size = resp_len * MBOX_WORD_BYTE; 581 flush_dcache_range(addr, *ret_size); 582 583 if (status != MBOX_RET_OK) { 584 *mbox_error = -status; 585 return INTEL_SIP_SMC_STATUS_ERROR; 586 } 587 588 return INTEL_SIP_SMC_STATUS_OK; 589 } 590 591 /* Miscellaneous HPS services */ 592 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 593 { 594 int status = 0; 595 596 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 597 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 598 status = socfpga_bridges_enable((uint32_t)mask); 599 } else { 600 status = socfpga_bridges_enable(~0); 601 } 602 } else { 603 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 604 status = socfpga_bridges_disable((uint32_t)mask); 605 } else { 606 status = socfpga_bridges_disable(~0); 607 } 608 } 609 610 if (status < 0) { 611 return INTEL_SIP_SMC_STATUS_ERROR; 612 } 613 614 return INTEL_SIP_SMC_STATUS_OK; 615 } 616 617 /* 618 * This function is responsible for handling all SiP calls from the NS world 619 */ 620 621 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 622 u_register_t x1, 623 u_register_t x2, 624 u_register_t x3, 625 u_register_t x4, 626 void *cookie, 627 void *handle, 628 u_register_t flags) 629 { 630 uint32_t retval = 0, completed_addr[3]; 631 uint32_t retval2 = 0; 632 uint32_t mbox_error = 0; 633 uint64_t retval64, rsu_respbuf[9]; 634 int status = INTEL_SIP_SMC_STATUS_OK; 635 int mbox_status; 636 unsigned int len_in_resp; 637 u_register_t x5, x6, x7; 638 639 switch (smc_fid) { 640 case SIP_SVC_UID: 641 /* Return UID to the caller */ 642 SMC_UUID_RET(handle, intl_svc_uid); 643 644 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 645 status = intel_mailbox_fpga_config_isdone(x1); 646 SMC_RET4(handle, status, 0, 0, 0); 647 648 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 649 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 650 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 651 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 652 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 653 654 case INTEL_SIP_SMC_FPGA_CONFIG_START: 655 status = intel_fpga_config_start(x1); 656 SMC_RET4(handle, status, 0, 0, 0); 657 658 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 659 status = intel_fpga_config_write(x1, x2); 660 SMC_RET4(handle, status, 0, 0, 0); 661 662 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 663 status = intel_fpga_config_completed_write(completed_addr, 664 &retval, &rcv_id); 665 switch (retval) { 666 case 1: 667 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 668 completed_addr[0], 0, 0); 669 670 case 2: 671 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 672 completed_addr[0], 673 completed_addr[1], 0); 674 675 case 3: 676 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 677 completed_addr[0], 678 completed_addr[1], 679 completed_addr[2]); 680 681 case 0: 682 SMC_RET4(handle, status, 0, 0, 0); 683 684 default: 685 mailbox_clear_response(); 686 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 687 } 688 689 case INTEL_SIP_SMC_REG_READ: 690 status = intel_secure_reg_read(x1, &retval); 691 SMC_RET3(handle, status, retval, x1); 692 693 case INTEL_SIP_SMC_REG_WRITE: 694 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 695 SMC_RET3(handle, status, retval, x1); 696 697 case INTEL_SIP_SMC_REG_UPDATE: 698 status = intel_secure_reg_update(x1, (uint32_t)x2, 699 (uint32_t)x3, &retval); 700 SMC_RET3(handle, status, retval, x1); 701 702 case INTEL_SIP_SMC_RSU_STATUS: 703 status = intel_rsu_status(rsu_respbuf, 704 ARRAY_SIZE(rsu_respbuf)); 705 if (status) { 706 SMC_RET1(handle, status); 707 } else { 708 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 709 rsu_respbuf[2], rsu_respbuf[3]); 710 } 711 712 case INTEL_SIP_SMC_RSU_UPDATE: 713 status = intel_rsu_update(x1); 714 SMC_RET1(handle, status); 715 716 case INTEL_SIP_SMC_RSU_NOTIFY: 717 status = intel_rsu_notify(x1); 718 SMC_RET1(handle, status); 719 720 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 721 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 722 ARRAY_SIZE(rsu_respbuf), &retval); 723 if (status) { 724 SMC_RET1(handle, status); 725 } else { 726 SMC_RET2(handle, status, retval); 727 } 728 729 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 730 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 731 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 732 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 733 734 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 735 status = intel_rsu_copy_dcmf_version(x1, x2); 736 SMC_RET1(handle, status); 737 738 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 739 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 740 ((uint64_t)rsu_dcmf_stat[3] << 48) | 741 ((uint64_t)rsu_dcmf_stat[2] << 32) | 742 ((uint64_t)rsu_dcmf_stat[1] << 16) | 743 rsu_dcmf_stat[0]); 744 745 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 746 status = intel_rsu_copy_dcmf_status(x1); 747 SMC_RET1(handle, status); 748 749 case INTEL_SIP_SMC_RSU_MAX_RETRY: 750 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 751 752 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 753 rsu_max_retry = x1; 754 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 755 756 case INTEL_SIP_SMC_ECC_DBE: 757 status = intel_ecc_dbe_notification(x1); 758 SMC_RET1(handle, status); 759 760 case INTEL_SIP_SMC_SERVICE_COMPLETED: 761 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 762 &len_in_resp, &mbox_error); 763 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 764 765 case INTEL_SIP_SMC_FIRMWARE_VERSION: 766 status = intel_smc_fw_version(&retval); 767 SMC_RET2(handle, status, retval); 768 769 case INTEL_SIP_SMC_MBOX_SEND_CMD: 770 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 771 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 772 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, 773 (uint32_t *)x5, x6, &mbox_status, 774 &len_in_resp); 775 SMC_RET3(handle, status, mbox_status, len_in_resp); 776 777 case INTEL_SIP_SMC_GET_USERCODE: 778 status = intel_smc_get_usercode(&retval); 779 SMC_RET2(handle, status, retval); 780 781 case INTEL_SIP_SMC_FCS_CRYPTION: 782 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 783 784 if (x1 == FCS_MODE_DECRYPT) { 785 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 786 } else if (x1 == FCS_MODE_ENCRYPT) { 787 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 788 } else { 789 status = INTEL_SIP_SMC_STATUS_REJECTED; 790 } 791 792 SMC_RET3(handle, status, x4, x5); 793 794 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 795 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 796 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 797 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 798 799 if (x3 == FCS_MODE_DECRYPT) { 800 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 801 (uint32_t *) &x7, &mbox_error); 802 } else if (x3 == FCS_MODE_ENCRYPT) { 803 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 804 (uint32_t *) &x7, &mbox_error); 805 } else { 806 status = INTEL_SIP_SMC_STATUS_REJECTED; 807 } 808 809 SMC_RET4(handle, status, mbox_error, x6, x7); 810 811 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 812 status = intel_fcs_random_number_gen(x1, &retval64, 813 &mbox_error); 814 SMC_RET4(handle, status, mbox_error, x1, retval64); 815 816 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 817 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 818 &send_id); 819 SMC_RET1(handle, status); 820 821 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 822 status = intel_fcs_send_cert(x1, x2, &send_id); 823 SMC_RET1(handle, status); 824 825 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 826 status = intel_fcs_get_provision_data(&send_id); 827 SMC_RET1(handle, status); 828 829 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 830 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 831 &mbox_error); 832 SMC_RET2(handle, status, mbox_error); 833 834 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 835 status = intel_hps_set_bridges(x1, x2); 836 SMC_RET1(handle, status); 837 838 case INTEL_SIP_SMC_HWMON_READTEMP: 839 status = intel_hwmon_readtemp(x1, &retval); 840 SMC_RET2(handle, status, retval); 841 842 case INTEL_SIP_SMC_HWMON_READVOLT: 843 status = intel_hwmon_readvolt(x1, &retval); 844 SMC_RET2(handle, status, retval); 845 846 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 847 status = intel_fcs_sigma_teardown(x1, &mbox_error); 848 SMC_RET2(handle, status, mbox_error); 849 850 case INTEL_SIP_SMC_FCS_CHIP_ID: 851 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 852 SMC_RET4(handle, status, mbox_error, retval, retval2); 853 854 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 855 status = intel_fcs_attestation_subkey(x1, x2, x3, 856 (uint32_t *) &x4, &mbox_error); 857 SMC_RET4(handle, status, mbox_error, x3, x4); 858 859 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 860 status = intel_fcs_get_measurement(x1, x2, x3, 861 (uint32_t *) &x4, &mbox_error); 862 SMC_RET4(handle, status, mbox_error, x3, x4); 863 864 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 865 status = intel_fcs_get_attestation_cert(x1, x2, 866 (uint32_t *) &x3, &mbox_error); 867 SMC_RET4(handle, status, mbox_error, x2, x3); 868 869 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 870 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 871 SMC_RET2(handle, status, mbox_error); 872 873 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 874 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 875 SMC_RET3(handle, status, mbox_error, retval); 876 877 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 878 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 879 SMC_RET2(handle, status, mbox_error); 880 881 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 882 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 883 SMC_RET1(handle, status); 884 885 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 886 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 887 (uint32_t *) &x4, &mbox_error); 888 SMC_RET4(handle, status, mbox_error, x3, x4); 889 890 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 891 status = intel_fcs_remove_crypto_service_key(x1, x2, 892 &mbox_error); 893 SMC_RET2(handle, status, mbox_error); 894 895 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 896 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 897 (uint32_t *) &x4, &mbox_error); 898 SMC_RET4(handle, status, mbox_error, x3, x4); 899 900 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 901 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 902 status = intel_fcs_get_digest_init(x1, x2, x3, 903 x4, x5, &mbox_error); 904 SMC_RET2(handle, status, mbox_error); 905 906 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 907 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 908 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 909 status = intel_fcs_get_digest_finalize(x1, x2, x3, 910 x4, x5, (uint32_t *) &x6, &mbox_error); 911 SMC_RET4(handle, status, mbox_error, x5, x6); 912 913 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 914 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 915 status = intel_fcs_mac_verify_init(x1, x2, x3, 916 x4, x5, &mbox_error); 917 SMC_RET2(handle, status, mbox_error); 918 919 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 920 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 921 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 922 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 923 status = intel_fcs_mac_verify_finalize(x1, x2, x3, 924 x4, x5, (uint32_t *) &x6, x7, &mbox_error); 925 SMC_RET4(handle, status, mbox_error, x5, x6); 926 927 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 928 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 929 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 930 x4, x5, &mbox_error); 931 SMC_RET2(handle, status, mbox_error); 932 933 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 934 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 935 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 936 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 937 x3, x4, x5, (uint32_t *) &x6, false, 938 &mbox_error); 939 SMC_RET4(handle, status, mbox_error, x5, x6); 940 941 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 942 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 943 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 944 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 945 x3, x4, x5, (uint32_t *) &x6, true, 946 &mbox_error); 947 SMC_RET4(handle, status, mbox_error, x5, x6); 948 949 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 950 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 951 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 952 x4, x5, &mbox_error); 953 SMC_RET2(handle, status, mbox_error); 954 955 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 956 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 957 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 958 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 959 x4, x5, (uint32_t *) &x6, &mbox_error); 960 SMC_RET4(handle, status, mbox_error, x5, x6); 961 962 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 963 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 964 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 965 x4, x5, &mbox_error); 966 SMC_RET2(handle, status, mbox_error); 967 968 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 969 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 970 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 971 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 972 x4, x5, (uint32_t *) &x6, &mbox_error); 973 SMC_RET4(handle, status, mbox_error, x5, x6); 974 975 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 976 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 977 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 978 x4, x5, &mbox_error); 979 SMC_RET2(handle, status, mbox_error); 980 981 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 982 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 983 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 984 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 985 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 986 x1, x2, x3, x4, x5, (uint32_t *) &x6, 987 x7, false, &mbox_error); 988 SMC_RET4(handle, status, mbox_error, x5, x6); 989 990 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 991 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 992 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 993 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 994 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 995 x1, x2, x3, x4, x5, (uint32_t *) &x6, 996 x7, true, &mbox_error); 997 SMC_RET4(handle, status, mbox_error, x5, x6); 998 999 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1000 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1001 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1002 x4, x5, &mbox_error); 1003 SMC_RET2(handle, status, mbox_error); 1004 1005 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1006 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1007 (uint32_t *) &x4, &mbox_error); 1008 SMC_RET4(handle, status, mbox_error, x3, x4); 1009 1010 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1011 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1012 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1013 x4, x5, &mbox_error); 1014 SMC_RET2(handle, status, mbox_error); 1015 1016 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1017 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1018 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1019 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1020 x4, x5, (uint32_t *) &x6, &mbox_error); 1021 SMC_RET4(handle, status, mbox_error, x5, x6); 1022 1023 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1024 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1025 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1026 &mbox_error); 1027 SMC_RET2(handle, status, mbox_error); 1028 1029 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1030 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1031 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1032 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1033 x5, x6, false, &send_id); 1034 SMC_RET1(handle, status); 1035 1036 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1037 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1038 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1039 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1040 x5, x6, true, &send_id); 1041 SMC_RET1(handle, status); 1042 1043 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1044 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1045 &mbox_error); 1046 SMC_RET4(handle, status, mbox_error, x1, retval64); 1047 1048 case INTEL_SIP_SMC_SVC_VERSION: 1049 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1050 SIP_SVC_VERSION_MAJOR, 1051 SIP_SVC_VERSION_MINOR); 1052 1053 default: 1054 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1055 cookie, handle, flags); 1056 } 1057 } 1058 1059 uintptr_t sip_smc_handler(uint32_t smc_fid, 1060 u_register_t x1, 1061 u_register_t x2, 1062 u_register_t x3, 1063 u_register_t x4, 1064 void *cookie, 1065 void *handle, 1066 u_register_t flags) 1067 { 1068 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1069 1070 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1071 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1072 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1073 cookie, handle, flags); 1074 } else { 1075 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1076 cookie, handle, flags); 1077 } 1078 } 1079 1080 DECLARE_RT_SVC( 1081 socfpga_sip_svc, 1082 OEN_SIP_START, 1083 OEN_SIP_END, 1084 SMC_TYPE_FAST, 1085 NULL, 1086 sip_smc_handler 1087 ); 1088 1089 DECLARE_RT_SVC( 1090 socfpga_sip_svc_std, 1091 OEN_SIP_START, 1092 OEN_SIP_END, 1093 SMC_TYPE_YIELD, 1094 NULL, 1095 sip_smc_handler 1096 ); 1097