1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_mailbox.h" 14 #include "socfpga_sip_svc.h" 15 16 /* Number of SiP Calls implemented */ 17 #define SIP_NUM_CALLS 0x3 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static int current_block; 23 static int read_block; 24 static int current_buffer; 25 static int send_id; 26 static int rcv_id; 27 static int max_blocks; 28 static uint32_t bytes_per_block; 29 static uint32_t blocks_submitted; 30 31 struct fpga_config_info { 32 uint32_t addr; 33 int size; 34 int size_written; 35 uint32_t write_requested; 36 int subblocks_sent; 37 int block_number; 38 }; 39 40 /* SiP Service UUID */ 41 DEFINE_SVC_UUID2(intl_svc_uid, 42 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 43 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 44 45 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 46 uint64_t x1, 47 uint64_t x2, 48 uint64_t x3, 49 uint64_t x4, 50 void *cookie, 51 void *handle, 52 uint64_t flags) 53 { 54 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 55 SMC_RET1(handle, SMC_UNK); 56 } 57 58 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 59 60 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 61 { 62 uint32_t args[3]; 63 64 while (max_blocks > 0 && buffer->size > buffer->size_written) { 65 args[0] = (1<<8); 66 args[1] = buffer->addr + buffer->size_written; 67 if (buffer->size - buffer->size_written <= bytes_per_block) { 68 args[2] = buffer->size - buffer->size_written; 69 current_buffer++; 70 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 71 } else 72 args[2] = bytes_per_block; 73 74 buffer->size_written += args[2]; 75 mailbox_send_cmd_async( 76 send_id++ % MBOX_MAX_JOB_ID, 77 MBOX_RECONFIG_DATA, 78 args, 3, 0); 79 80 buffer->subblocks_sent++; 81 max_blocks--; 82 } 83 84 return !max_blocks; 85 } 86 87 static int intel_fpga_sdm_write_all(void) 88 { 89 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 90 if (intel_fpga_sdm_write_buffer( 91 &fpga_config_buffers[current_buffer])) 92 break; 93 return 0; 94 } 95 96 static uint32_t intel_mailbox_fpga_config_isdone(void) 97 { 98 uint32_t ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); 99 100 if (ret) { 101 if (ret == MBOX_CFGSTAT_STATE_CONFIG) 102 return INTEL_SIP_SMC_STATUS_BUSY; 103 else 104 return INTEL_SIP_SMC_STATUS_ERROR; 105 } 106 107 return INTEL_SIP_SMC_STATUS_OK; 108 } 109 110 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 111 { 112 int i; 113 114 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 115 if (fpga_config_buffers[i].block_number == current_block) { 116 fpga_config_buffers[i].subblocks_sent--; 117 if (fpga_config_buffers[i].subblocks_sent == 0 118 && fpga_config_buffers[i].size <= 119 fpga_config_buffers[i].size_written) { 120 fpga_config_buffers[i].write_requested = 0; 121 current_block++; 122 *buffer_addr_completed = 123 fpga_config_buffers[i].addr; 124 return 0; 125 } 126 } 127 } 128 129 return -1; 130 } 131 132 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 133 uint32_t *count) 134 { 135 uint32_t status = INTEL_SIP_SMC_STATUS_OK; 136 *count = 0; 137 int resp_len = 0; 138 uint32_t resp[5]; 139 int all_completed = 1; 140 141 while (*count < 3) { 142 143 resp_len = mailbox_read_response(rcv_id % MBOX_MAX_JOB_ID, 144 resp, sizeof(resp) / sizeof(resp[0])); 145 146 if (resp_len < 0) 147 break; 148 149 max_blocks++; 150 rcv_id++; 151 152 if (mark_last_buffer_xfer_completed( 153 &completed_addr[*count]) == 0) 154 *count = *count + 1; 155 else 156 break; 157 } 158 159 if (*count <= 0) { 160 if (resp_len != MBOX_NO_RESPONSE && 161 resp_len != MBOX_TIMEOUT && resp_len != 0) { 162 mailbox_clear_response(); 163 return INTEL_SIP_SMC_STATUS_ERROR; 164 } 165 166 *count = 0; 167 } 168 169 intel_fpga_sdm_write_all(); 170 171 if (*count > 0) 172 status = INTEL_SIP_SMC_STATUS_OK; 173 else if (*count == 0) 174 status = INTEL_SIP_SMC_STATUS_BUSY; 175 176 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 177 if (fpga_config_buffers[i].write_requested != 0) { 178 all_completed = 0; 179 break; 180 } 181 } 182 183 if (all_completed == 1) 184 return INTEL_SIP_SMC_STATUS_OK; 185 186 return status; 187 } 188 189 static int intel_fpga_config_start(uint32_t config_type) 190 { 191 uint32_t response[3]; 192 int status = 0; 193 194 mailbox_clear_response(); 195 196 mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0); 197 198 status = mailbox_send_cmd(1, MBOX_RECONFIG, 0, 0, 0, 199 response, sizeof(response) / sizeof(response[0])); 200 201 if (status < 0) 202 return status; 203 204 max_blocks = response[0]; 205 bytes_per_block = response[1]; 206 207 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 208 fpga_config_buffers[i].size = 0; 209 fpga_config_buffers[i].size_written = 0; 210 fpga_config_buffers[i].addr = 0; 211 fpga_config_buffers[i].write_requested = 0; 212 fpga_config_buffers[i].block_number = 0; 213 fpga_config_buffers[i].subblocks_sent = 0; 214 } 215 216 blocks_submitted = 0; 217 current_block = 0; 218 read_block = 0; 219 current_buffer = 0; 220 send_id = 0; 221 rcv_id = 0; 222 223 return 0; 224 } 225 226 static bool is_fpga_config_buffer_full(void) 227 { 228 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 229 if (!fpga_config_buffers[i].write_requested) 230 return false; 231 return true; 232 } 233 234 static bool is_address_in_ddr_range(uint64_t addr) 235 { 236 if (addr >= DRAM_BASE && addr <= DRAM_BASE + DRAM_SIZE) 237 return true; 238 239 return false; 240 } 241 242 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 243 { 244 int i; 245 246 intel_fpga_sdm_write_all(); 247 248 if (!is_address_in_ddr_range(mem) || 249 !is_address_in_ddr_range(mem + size) || 250 is_fpga_config_buffer_full()) 251 return INTEL_SIP_SMC_STATUS_REJECTED; 252 253 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 254 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 255 256 if (!fpga_config_buffers[j].write_requested) { 257 fpga_config_buffers[j].addr = mem; 258 fpga_config_buffers[j].size = size; 259 fpga_config_buffers[j].size_written = 0; 260 fpga_config_buffers[j].write_requested = 1; 261 fpga_config_buffers[j].block_number = 262 blocks_submitted++; 263 fpga_config_buffers[j].subblocks_sent = 0; 264 break; 265 } 266 } 267 268 if (is_fpga_config_buffer_full()) 269 return INTEL_SIP_SMC_STATUS_BUSY; 270 271 return INTEL_SIP_SMC_STATUS_OK; 272 } 273 274 static int is_out_of_sec_range(uint64_t reg_addr) 275 { 276 switch (reg_addr) { 277 case(0xF8011100): /* ECCCTRL1 */ 278 case(0xF8011104): /* ECCCTRL2 */ 279 case(0xF8011110): /* ERRINTEN */ 280 case(0xF8011114): /* ERRINTENS */ 281 case(0xF8011118): /* ERRINTENR */ 282 case(0xF801111C): /* INTMODE */ 283 case(0xF8011120): /* INTSTAT */ 284 case(0xF8011124): /* DIAGINTTEST */ 285 case(0xF801112C): /* DERRADDRA */ 286 case(0xFFD12028): /* SDMMCGRP_CTRL */ 287 case(0xFFD12044): /* EMAC0 */ 288 case(0xFFD12048): /* EMAC1 */ 289 case(0xFFD1204C): /* EMAC2 */ 290 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 291 case(0xFFD12094): /* ECC_INT_MASK_SET */ 292 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 293 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 294 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 295 case(0xFFD120C0): /* NOC_TIMEOUT */ 296 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 297 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 298 case(0xFFD120D0): /* NOC_IDLEACK */ 299 case(0xFFD120D4): /* NOC_IDLESTATUS */ 300 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 301 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 302 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 303 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 304 return 0; 305 306 default: 307 break; 308 } 309 310 return -1; 311 } 312 313 /* Secure register access */ 314 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 315 { 316 if (is_out_of_sec_range(reg_addr)) 317 return INTEL_SIP_SMC_STATUS_ERROR; 318 319 *retval = mmio_read_32(reg_addr); 320 321 return INTEL_SIP_SMC_STATUS_OK; 322 } 323 324 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 325 uint32_t *retval) 326 { 327 if (is_out_of_sec_range(reg_addr)) 328 return INTEL_SIP_SMC_STATUS_ERROR; 329 330 mmio_write_32(reg_addr, val); 331 332 return intel_secure_reg_read(reg_addr, retval); 333 } 334 335 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 336 uint32_t val, uint32_t *retval) 337 { 338 if (!intel_secure_reg_read(reg_addr, retval)) { 339 *retval &= ~mask; 340 *retval |= val; 341 return intel_secure_reg_write(reg_addr, *retval, retval); 342 } 343 344 return INTEL_SIP_SMC_STATUS_ERROR; 345 } 346 347 /* 348 * This function is responsible for handling all SiP calls from the NS world 349 */ 350 351 uintptr_t sip_smc_handler(uint32_t smc_fid, 352 u_register_t x1, 353 u_register_t x2, 354 u_register_t x3, 355 u_register_t x4, 356 void *cookie, 357 void *handle, 358 u_register_t flags) 359 { 360 uint32_t val = 0; 361 uint32_t status = INTEL_SIP_SMC_STATUS_OK; 362 uint32_t completed_addr[3]; 363 uint32_t count = 0; 364 365 switch (smc_fid) { 366 case SIP_SVC_UID: 367 /* Return UID to the caller */ 368 SMC_UUID_RET(handle, intl_svc_uid); 369 370 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 371 status = intel_mailbox_fpga_config_isdone(); 372 SMC_RET4(handle, status, 0, 0, 0); 373 374 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 375 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 376 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 377 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 378 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 379 380 case INTEL_SIP_SMC_FPGA_CONFIG_START: 381 status = intel_fpga_config_start(x1); 382 SMC_RET4(handle, status, 0, 0, 0); 383 384 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 385 status = intel_fpga_config_write(x1, x2); 386 SMC_RET4(handle, status, 0, 0, 0); 387 388 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 389 status = intel_fpga_config_completed_write(completed_addr, 390 &count); 391 switch (count) { 392 case 1: 393 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 394 completed_addr[0], 0, 0); 395 396 case 2: 397 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 398 completed_addr[0], 399 completed_addr[1], 0); 400 401 case 3: 402 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 403 completed_addr[0], 404 completed_addr[1], 405 completed_addr[2]); 406 407 case 0: 408 SMC_RET4(handle, status, 0, 0, 0); 409 410 default: 411 mailbox_clear_response(); 412 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 413 } 414 415 case INTEL_SIP_SMC_REG_READ: 416 status = intel_secure_reg_read(x1, &val); 417 SMC_RET3(handle, status, val, x1); 418 419 case INTEL_SIP_SMC_REG_WRITE: 420 status = intel_secure_reg_write(x1, (uint32_t)x2, &val); 421 SMC_RET3(handle, status, val, x1); 422 423 case INTEL_SIP_SMC_REG_UPDATE: 424 status = intel_secure_reg_update(x1, (uint32_t)x2, 425 (uint32_t)x3, &val); 426 SMC_RET3(handle, status, val, x1); 427 428 default: 429 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 430 cookie, handle, flags); 431 } 432 } 433 434 DECLARE_RT_SVC( 435 socfpga_sip_svc, 436 OEN_SIP_START, 437 OEN_SIP_END, 438 SMC_TYPE_FAST, 439 NULL, 440 sip_smc_handler 441 ); 442 443 DECLARE_RT_SVC( 444 socfpga_sip_svc_std, 445 OEN_SIP_START, 446 OEN_SIP_END, 447 SMC_TYPE_YIELD, 448 NULL, 449 sip_smc_handler 450 ); 451