1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <common/debug.h> 11 #include <common/runtime_svc.h> 12 #include <lib/mmio.h> 13 #include <tools_share/uuid.h> 14 15 #include "socfpga_fcs.h" 16 #include "socfpga_mailbox.h" 17 #include "socfpga_plat_def.h" 18 #include "socfpga_reset_manager.h" 19 #include "socfpga_sip_svc.h" 20 #include "socfpga_system_manager.h" 21 22 /* Total buffer the driver can hold */ 23 #define FPGA_CONFIG_BUFFER_SIZE 4 24 25 static config_type request_type = NO_REQUEST; 26 static int current_block, current_buffer; 27 static int read_block, max_blocks; 28 static uint32_t send_id, rcv_id; 29 static uint32_t bytes_per_block, blocks_submitted; 30 static bool bridge_disable; 31 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 32 static uint32_t g_remapper_bypass; 33 #endif 34 35 /* RSU static variables */ 36 static uint32_t rsu_dcmf_ver[4] = {0}; 37 static uint16_t rsu_dcmf_stat[4] = {0}; 38 static uint32_t rsu_max_retry; 39 40 /* SiP Service UUID */ 41 DEFINE_SVC_UUID2(intl_svc_uid, 42 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 43 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 44 45 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 46 uint64_t x1, 47 uint64_t x2, 48 uint64_t x3, 49 uint64_t x4, 50 void *cookie, 51 void *handle, 52 uint64_t flags) 53 { 54 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 55 SMC_RET1(handle, SMC_UNK); 56 } 57 58 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 59 60 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 61 { 62 uint32_t args[3]; 63 64 while (max_blocks > 0 && buffer->size > buffer->size_written) { 65 args[0] = (1<<8); 66 args[1] = buffer->addr + buffer->size_written; 67 if (buffer->size - buffer->size_written <= bytes_per_block) { 68 args[2] = buffer->size - buffer->size_written; 69 current_buffer++; 70 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 71 } else { 72 args[2] = bytes_per_block; 73 } 74 75 buffer->size_written += args[2]; 76 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 77 3U, CMD_INDIRECT); 78 79 buffer->subblocks_sent++; 80 max_blocks--; 81 } 82 83 return !max_blocks; 84 } 85 86 static int intel_fpga_sdm_write_all(void) 87 { 88 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 89 if (intel_fpga_sdm_write_buffer( 90 &fpga_config_buffers[current_buffer])) { 91 break; 92 } 93 } 94 return 0; 95 } 96 97 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t *err_states) 98 { 99 uint32_t ret; 100 101 if (err_states == NULL) 102 return INTEL_SIP_SMC_STATUS_REJECTED; 103 104 switch (request_type) { 105 case RECONFIGURATION: 106 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 107 true, err_states); 108 break; 109 case BITSTREAM_AUTH: 110 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 111 false, err_states); 112 break; 113 default: 114 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 115 false, err_states); 116 break; 117 } 118 119 if (ret != 0U) { 120 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 121 return INTEL_SIP_SMC_STATUS_BUSY; 122 } else { 123 request_type = NO_REQUEST; 124 return INTEL_SIP_SMC_STATUS_ERROR; 125 } 126 } 127 128 if (bridge_disable != 0U) { 129 socfpga_bridges_enable(~0); /* Enable bridge */ 130 bridge_disable = false; 131 } 132 request_type = NO_REQUEST; 133 134 return INTEL_SIP_SMC_STATUS_OK; 135 } 136 137 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 138 { 139 int i; 140 141 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 142 if (fpga_config_buffers[i].block_number == current_block) { 143 fpga_config_buffers[i].subblocks_sent--; 144 if (fpga_config_buffers[i].subblocks_sent == 0 145 && fpga_config_buffers[i].size <= 146 fpga_config_buffers[i].size_written) { 147 fpga_config_buffers[i].write_requested = 0; 148 current_block++; 149 *buffer_addr_completed = 150 fpga_config_buffers[i].addr; 151 return 0; 152 } 153 } 154 } 155 156 return -1; 157 } 158 159 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 160 uint32_t *count, uint32_t *job_id) 161 { 162 uint32_t resp[5]; 163 unsigned int resp_len = ARRAY_SIZE(resp); 164 int status = INTEL_SIP_SMC_STATUS_OK; 165 int all_completed = 1; 166 *count = 0; 167 168 while (*count < 3) { 169 170 status = mailbox_read_response(job_id, 171 resp, &resp_len); 172 173 if (status < 0) { 174 break; 175 } 176 177 max_blocks++; 178 179 if (mark_last_buffer_xfer_completed( 180 &completed_addr[*count]) == 0) { 181 *count = *count + 1; 182 } else { 183 break; 184 } 185 } 186 187 if (*count <= 0) { 188 if (status != MBOX_NO_RESPONSE && 189 status != MBOX_TIMEOUT && resp_len != 0) { 190 mailbox_clear_response(); 191 request_type = NO_REQUEST; 192 return INTEL_SIP_SMC_STATUS_ERROR; 193 } 194 195 *count = 0; 196 } 197 198 intel_fpga_sdm_write_all(); 199 200 if (*count > 0) { 201 status = INTEL_SIP_SMC_STATUS_OK; 202 } else if (*count == 0) { 203 status = INTEL_SIP_SMC_STATUS_BUSY; 204 } 205 206 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 207 if (fpga_config_buffers[i].write_requested != 0) { 208 all_completed = 0; 209 break; 210 } 211 } 212 213 if (all_completed == 1) { 214 return INTEL_SIP_SMC_STATUS_OK; 215 } 216 217 return status; 218 } 219 220 static int intel_fpga_config_start(uint32_t flag) 221 { 222 uint32_t argument = 0x1; 223 uint32_t response[3]; 224 int status = 0; 225 unsigned int size = 0; 226 unsigned int resp_len = ARRAY_SIZE(response); 227 228 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 229 /* 230 * To trigger isolation 231 * FPGA configuration complete signal should be de-asserted 232 */ 233 INFO("SOCFPGA: Request SDM to trigger isolation\n"); 234 status = mailbox_send_fpga_config_comp(); 235 236 if (status < 0) { 237 INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n"); 238 } 239 #endif 240 241 request_type = RECONFIGURATION; 242 243 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 244 bridge_disable = true; 245 } 246 247 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 248 size = 1; 249 bridge_disable = false; 250 request_type = BITSTREAM_AUTH; 251 } 252 253 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 254 intel_smmu_hps_remapper_init(0U); 255 #endif 256 257 mailbox_clear_response(); 258 259 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 260 CMD_CASUAL, NULL, NULL); 261 262 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 263 CMD_CASUAL, response, &resp_len); 264 265 if (status < 0) { 266 bridge_disable = false; 267 request_type = NO_REQUEST; 268 return INTEL_SIP_SMC_STATUS_ERROR; 269 } 270 271 max_blocks = response[0]; 272 bytes_per_block = response[1]; 273 274 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 275 fpga_config_buffers[i].size = 0; 276 fpga_config_buffers[i].size_written = 0; 277 fpga_config_buffers[i].addr = 0; 278 fpga_config_buffers[i].write_requested = 0; 279 fpga_config_buffers[i].block_number = 0; 280 fpga_config_buffers[i].subblocks_sent = 0; 281 } 282 283 blocks_submitted = 0; 284 current_block = 0; 285 read_block = 0; 286 current_buffer = 0; 287 288 /* Disable bridge on full reconfiguration */ 289 if (bridge_disable) { 290 socfpga_bridges_disable(~0); 291 } 292 293 return INTEL_SIP_SMC_STATUS_OK; 294 } 295 296 static bool is_fpga_config_buffer_full(void) 297 { 298 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 299 if (!fpga_config_buffers[i].write_requested) { 300 return false; 301 } 302 } 303 return true; 304 } 305 306 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 307 { 308 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 309 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 310 311 if (!addr && !size) { 312 return true; 313 } 314 if (size > (UINT64_MAX - addr)) { 315 return false; 316 } 317 if (addr < BL31_LIMIT) { 318 return false; 319 } 320 if (dram_region_end > dram_max_sz) { 321 return false; 322 } 323 324 return true; 325 } 326 327 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 328 { 329 int i; 330 331 intel_fpga_sdm_write_all(); 332 333 if (!is_address_in_ddr_range(mem, size) || 334 is_fpga_config_buffer_full()) { 335 return INTEL_SIP_SMC_STATUS_REJECTED; 336 } 337 338 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 339 intel_smmu_hps_remapper_init(&mem); 340 #endif 341 342 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 343 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 344 345 if (!fpga_config_buffers[j].write_requested) { 346 fpga_config_buffers[j].addr = mem; 347 fpga_config_buffers[j].size = size; 348 fpga_config_buffers[j].size_written = 0; 349 fpga_config_buffers[j].write_requested = 1; 350 fpga_config_buffers[j].block_number = 351 blocks_submitted++; 352 fpga_config_buffers[j].subblocks_sent = 0; 353 break; 354 } 355 } 356 357 if (is_fpga_config_buffer_full()) { 358 return INTEL_SIP_SMC_STATUS_BUSY; 359 } 360 361 return INTEL_SIP_SMC_STATUS_OK; 362 } 363 364 static int is_out_of_sec_range(uint64_t reg_addr) 365 { 366 #if DEBUG 367 return 0; 368 #endif 369 370 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 371 switch (reg_addr) { 372 case(0xF8011100): /* ECCCTRL1 */ 373 case(0xF8011104): /* ECCCTRL2 */ 374 case(0xF8011110): /* ERRINTEN */ 375 case(0xF8011114): /* ERRINTENS */ 376 case(0xF8011118): /* ERRINTENR */ 377 case(0xF801111C): /* INTMODE */ 378 case(0xF8011120): /* INTSTAT */ 379 case(0xF8011124): /* DIAGINTTEST */ 380 case(0xF801112C): /* DERRADDRA */ 381 case(0xFA000000): /* SMMU SCR0 */ 382 case(0xFA000004): /* SMMU SCR1 */ 383 case(0xFA000400): /* SMMU NSCR0 */ 384 case(0xFA004000): /* SMMU SSD0_REG */ 385 case(0xFA000820): /* SMMU SMR8 */ 386 case(0xFA000c20): /* SMMU SCR8 */ 387 case(0xFA028000): /* SMMU CB8_SCTRL */ 388 case(0xFA001020): /* SMMU CBAR8 */ 389 case(0xFA028030): /* SMMU TCR_LPAE */ 390 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 391 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 392 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 393 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 394 case(0xFA028010): /* SMMU_CB8)TCR2 */ 395 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 396 case(0xFA001820): /* SMMU_CBA2R8 */ 397 case(0xFA000074): /* SMMU_STLBGSTATUS */ 398 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 399 case(0xFA000060): /* SMMU_STLBIALL */ 400 case(0xFA000070): /* SMMU_STLBGSYNC */ 401 case(0xFA028618): /* CB8_TLBALL */ 402 case(0xFA0287F0): /* CB8_TLBSYNC */ 403 case(0xFFD12028): /* SDMMCGRP_CTRL */ 404 case(0xFFD12044): /* EMAC0 */ 405 case(0xFFD12048): /* EMAC1 */ 406 case(0xFFD1204C): /* EMAC2 */ 407 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 408 case(0xFFD12094): /* ECC_INT_MASK_SET */ 409 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 410 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 411 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 412 case(0xFFD120C0): /* NOC_TIMEOUT */ 413 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 414 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 415 case(0xFFD120D0): /* NOC_IDLEACK */ 416 case(0xFFD120D4): /* NOC_IDLESTATUS */ 417 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 418 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 419 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 420 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 421 return 0; 422 #else 423 switch (reg_addr) { 424 425 case(0xF8011104): /* ECCCTRL2 */ 426 case(0xFFD12028): /* SDMMCGRP_CTRL */ 427 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 428 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 429 case(0xFFD120D0): /* NOC_IDLEACK */ 430 431 432 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 433 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 434 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 435 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 436 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 437 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 438 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 439 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 440 441 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */ 442 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 443 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 444 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 445 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 446 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 447 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 448 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 449 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 450 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 451 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 452 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 453 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 454 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 455 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 456 #endif 457 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 458 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 459 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 460 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 461 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 462 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 463 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 464 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 465 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 466 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 467 return 0; 468 469 default: 470 break; 471 } 472 473 return -1; 474 } 475 476 /* Secure register access */ 477 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 478 { 479 if (is_out_of_sec_range(reg_addr)) { 480 return INTEL_SIP_SMC_STATUS_ERROR; 481 } 482 483 *retval = mmio_read_32(reg_addr); 484 485 return INTEL_SIP_SMC_STATUS_OK; 486 } 487 488 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 489 uint32_t *retval) 490 { 491 if (is_out_of_sec_range(reg_addr)) { 492 return INTEL_SIP_SMC_STATUS_ERROR; 493 } 494 495 switch (reg_addr) { 496 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 497 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 498 mmio_write_16(reg_addr, val); 499 break; 500 default: 501 mmio_write_32(reg_addr, val); 502 break; 503 } 504 505 return intel_secure_reg_read(reg_addr, retval); 506 } 507 508 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 509 uint32_t val, uint32_t *retval) 510 { 511 if (!intel_secure_reg_read(reg_addr, retval)) { 512 *retval &= ~mask; 513 *retval |= val & mask; 514 return intel_secure_reg_write(reg_addr, *retval, retval); 515 } 516 517 return INTEL_SIP_SMC_STATUS_ERROR; 518 } 519 520 /* Intel Remote System Update (RSU) services */ 521 uint64_t intel_rsu_update_address; 522 523 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 524 { 525 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 526 return INTEL_SIP_SMC_RSU_ERROR; 527 } 528 529 return INTEL_SIP_SMC_STATUS_OK; 530 } 531 532 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf, 533 unsigned int respbuf_sz) 534 { 535 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) { 536 return INTEL_SIP_SMC_RSU_ERROR; 537 } 538 539 return INTEL_SIP_SMC_STATUS_OK; 540 } 541 542 uint32_t intel_rsu_update(uint64_t update_address) 543 { 544 if (update_address > SIZE_MAX) { 545 return INTEL_SIP_SMC_STATUS_REJECTED; 546 } 547 548 intel_rsu_update_address = update_address; 549 return INTEL_SIP_SMC_STATUS_OK; 550 } 551 552 static uint32_t intel_rsu_notify(uint32_t execution_stage) 553 { 554 if (mailbox_hps_stage_notify(execution_stage) < 0) { 555 return INTEL_SIP_SMC_RSU_ERROR; 556 } 557 558 return INTEL_SIP_SMC_STATUS_OK; 559 } 560 561 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 562 uint32_t *ret_stat) 563 { 564 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 565 return INTEL_SIP_SMC_RSU_ERROR; 566 } 567 568 *ret_stat = respbuf[8]; 569 return INTEL_SIP_SMC_STATUS_OK; 570 } 571 572 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 573 uint64_t dcmf_ver_3_2) 574 { 575 rsu_dcmf_ver[0] = dcmf_ver_1_0; 576 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 577 rsu_dcmf_ver[2] = dcmf_ver_3_2; 578 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 579 580 return INTEL_SIP_SMC_STATUS_OK; 581 } 582 583 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 584 { 585 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 586 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 587 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 588 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 589 590 return INTEL_SIP_SMC_STATUS_OK; 591 } 592 593 /* Intel HWMON services */ 594 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 595 { 596 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 597 return INTEL_SIP_SMC_STATUS_ERROR; 598 } 599 600 return INTEL_SIP_SMC_STATUS_OK; 601 } 602 603 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 604 { 605 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 606 return INTEL_SIP_SMC_STATUS_ERROR; 607 } 608 609 return INTEL_SIP_SMC_STATUS_OK; 610 } 611 612 /* Mailbox services */ 613 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 614 { 615 int status; 616 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 617 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 618 619 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 620 CMD_CASUAL, resp_data, &resp_len); 621 622 if (status < 0) { 623 return INTEL_SIP_SMC_STATUS_ERROR; 624 } 625 626 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 627 return INTEL_SIP_SMC_STATUS_ERROR; 628 } 629 630 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 631 632 return INTEL_SIP_SMC_STATUS_OK; 633 } 634 635 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 636 unsigned int len, uint32_t urgent, uint64_t response, 637 unsigned int resp_len, int *mbox_status, 638 unsigned int *len_in_resp) 639 { 640 *len_in_resp = 0; 641 *mbox_status = GENERIC_RESPONSE_ERROR; 642 643 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 644 return INTEL_SIP_SMC_STATUS_REJECTED; 645 } 646 647 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 648 (uint32_t *) response, &resp_len); 649 650 if (status < 0) { 651 *mbox_status = -status; 652 return INTEL_SIP_SMC_STATUS_ERROR; 653 } 654 655 *mbox_status = 0; 656 *len_in_resp = resp_len; 657 658 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 659 660 return INTEL_SIP_SMC_STATUS_OK; 661 } 662 663 static int intel_smc_get_usercode(uint32_t *user_code) 664 { 665 int status; 666 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 667 668 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 669 0U, CMD_CASUAL, user_code, &resp_len); 670 671 if (status < 0) { 672 return INTEL_SIP_SMC_STATUS_ERROR; 673 } 674 675 return INTEL_SIP_SMC_STATUS_OK; 676 } 677 678 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 679 uint32_t mode, uint32_t *job_id, 680 uint32_t *ret_size, uint32_t *mbox_error) 681 { 682 int status = 0; 683 uint32_t resp_len = size / MBOX_WORD_BYTE; 684 685 if (resp_len > MBOX_DATA_MAX_LEN) { 686 return INTEL_SIP_SMC_STATUS_REJECTED; 687 } 688 689 if (!is_address_in_ddr_range(addr, size)) { 690 return INTEL_SIP_SMC_STATUS_REJECTED; 691 } 692 693 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 694 status = mailbox_read_response_async(job_id, 695 NULL, (uint32_t *) addr, &resp_len, 0); 696 } else { 697 status = mailbox_read_response(job_id, 698 (uint32_t *) addr, &resp_len); 699 700 if (status == MBOX_NO_RESPONSE) { 701 status = MBOX_BUSY; 702 } 703 } 704 705 if (status == MBOX_NO_RESPONSE) { 706 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 707 } 708 709 if (status == MBOX_BUSY) { 710 return INTEL_SIP_SMC_STATUS_BUSY; 711 } 712 713 *ret_size = resp_len * MBOX_WORD_BYTE; 714 flush_dcache_range(addr, *ret_size); 715 716 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 717 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 718 *mbox_error = -status; 719 } else if (status != MBOX_RET_OK) { 720 *mbox_error = -status; 721 return INTEL_SIP_SMC_STATUS_ERROR; 722 } 723 724 return INTEL_SIP_SMC_STATUS_OK; 725 } 726 727 /* Miscellaneous HPS services */ 728 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 729 { 730 int status = 0; 731 732 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 733 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 734 status = socfpga_bridges_enable((uint32_t)mask); 735 } else { 736 status = socfpga_bridges_enable(~0); 737 } 738 } else { 739 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 740 status = socfpga_bridges_disable((uint32_t)mask); 741 } else { 742 status = socfpga_bridges_disable(~0); 743 } 744 } 745 746 if (status < 0) { 747 return INTEL_SIP_SMC_STATUS_ERROR; 748 } 749 750 return INTEL_SIP_SMC_STATUS_OK; 751 } 752 753 /* SDM SEU Error services */ 754 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 755 { 756 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 757 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 758 } 759 760 return INTEL_SIP_SMC_STATUS_OK; 761 } 762 763 /* SDM SAFE SEU Error inject services */ 764 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 765 { 766 if (mailbox_safe_inject_seu_err(command, len) < 0) { 767 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 768 } 769 770 return INTEL_SIP_SMC_STATUS_OK; 771 } 772 773 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 774 /* SMMU HPS Remapper */ 775 void intel_smmu_hps_remapper_init(uint64_t *mem) 776 { 777 /* Read out Bit 1 value */ 778 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 779 780 if ((remap == 0x00) && (g_remapper_bypass == 0x00)) { 781 /* Update DRAM Base address for SDM SMMU */ 782 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 783 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 784 *mem = *mem - DRAM_BASE; 785 } else { 786 *mem = *mem - DRAM_BASE; 787 } 788 } 789 790 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass) 791 { 792 /* Read out the JTAG-ID from boot scratch register */ 793 if (is_agilex5_A5F0() || is_agilex5_A5F4()) { 794 if (remapper_bypass == 0x01) { 795 g_remapper_bypass = remapper_bypass; 796 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0); 797 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0); 798 } 799 } 800 return INTEL_SIP_SMC_STATUS_OK; 801 } 802 #endif 803 804 #if SIP_SVC_V3 805 uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint32_t *ret_args) 806 { 807 uint8_t ret_args_len = 0U; 808 sdm_response_t *resp = (sdm_response_t *)resp_desc; 809 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 810 811 (void)cmd; 812 /* Returns 3 SMC arguments for SMC_RET3 */ 813 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 814 ret_args[ret_args_len++] = resp->err_code; 815 816 return ret_args_len; 817 } 818 819 uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint32_t *ret_args) 820 { 821 uint8_t ret_args_len = 0U; 822 sdm_response_t *resp = (sdm_response_t *)resp_desc; 823 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 824 825 (void)cmd; 826 /* Returns 3 SMC arguments for SMC_RET3 */ 827 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 828 ret_args[ret_args_len++] = resp->err_code; 829 ret_args[ret_args_len++] = resp->resp_data[0]; 830 831 return ret_args_len; 832 } 833 834 uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args) 835 { 836 uint8_t ret_args_len = 0U; 837 sdm_response_t *resp = (sdm_response_t *)resp_desc; 838 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 839 840 (void)cmd; 841 INFO("MBOX: %s: mailbox_err 0%x, nbytes_ret %d\n", 842 __func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE); 843 844 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 845 ret_args[ret_args_len++] = resp->err_code; 846 ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE; 847 848 return ret_args_len; 849 } 850 851 uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args) 852 { 853 uint8_t ret_args_len = 0U; 854 sdm_response_t *resp = (sdm_response_t *)resp_desc; 855 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 856 857 (void)cmd; 858 INFO("MBOX: %s: mailbox_err 0%x, data[0] 0x%x, data[1] 0x%x\n", 859 __func__, resp->err_code, resp->resp_data[0], resp->resp_data[1]); 860 861 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 862 ret_args[ret_args_len++] = resp->err_code; 863 ret_args[ret_args_len++] = resp->resp_data[0]; 864 ret_args[ret_args_len++] = resp->resp_data[1]; 865 866 return ret_args_len; 867 } 868 869 static uintptr_t smc_ret(void *handle, uint32_t *ret_args, uint32_t ret_args_len) 870 { 871 switch (ret_args_len) { 872 case SMC_RET_ARGS_ONE: 873 SMC_RET1(handle, ret_args[0]); 874 break; 875 876 case SMC_RET_ARGS_TWO: 877 SMC_RET2(handle, ret_args[0], ret_args[1]); 878 break; 879 880 case SMC_RET_ARGS_THREE: 881 SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]); 882 break; 883 884 case SMC_RET_ARGS_FOUR: 885 SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 886 break; 887 888 case SMC_RET_ARGS_FIVE: 889 SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 890 break; 891 892 default: 893 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 894 break; 895 } 896 } 897 898 /* 899 * This function is responsible for handling all SiP SVC V3 calls from the 900 * non-secure world. 901 */ 902 static uintptr_t sip_smc_handler_v3(uint32_t smc_fid, 903 u_register_t x1, 904 u_register_t x2, 905 u_register_t x3, 906 u_register_t x4, 907 void *cookie, 908 void *handle, 909 u_register_t flags) 910 { 911 int status = 0; 912 uint32_t mbox_error = 0U; 913 u_register_t x5, x6, x7, x8, x9, x10, x11; 914 915 /* Get all the SMC call arguments */ 916 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 917 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 918 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 919 x8 = SMC_GET_GP(handle, CTX_GPREG_X8); 920 x9 = SMC_GET_GP(handle, CTX_GPREG_X9); 921 x10 = SMC_GET_GP(handle, CTX_GPREG_X10); 922 x11 = SMC_GET_GP(handle, CTX_GPREG_X11); 923 924 INFO("MBOX: SVC_V3: x0 0x%x, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\n", 925 smc_fid, x1, x2, x3, x4, x5); 926 INFO("MBOX: SVC_V3: x6 0x%lx, x7 0x%lx, x8 0x%lx, x9 0x%lx, x10 0x%lx x11 0x%lx\n", 927 x6, x7, x8, x9, x10, x11); 928 929 switch (smc_fid) { 930 case ALTERA_SIP_SMC_ASYNC_RESP_POLL: 931 { 932 uint32_t ret_args[8] = {0}; 933 uint32_t ret_args_len; 934 935 status = mailbox_response_poll_v3(GET_CLIENT_ID(x1), 936 GET_JOB_ID(x1), 937 ret_args, 938 &ret_args_len); 939 /* Always reserve [0] index for command status. */ 940 ret_args[0] = status; 941 942 /* Return SMC call based on the number of return arguments */ 943 return smc_ret(handle, ret_args, ret_args_len); 944 } 945 946 case ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR: 947 { 948 /* TBD: Here now we don't need these CID and JID?? */ 949 uint8_t client_id = 0U; 950 uint8_t job_id = 0U; 951 uint64_t trans_id_bitmap[4] = {0U}; 952 953 status = mailbox_response_poll_on_intr_v3(&client_id, 954 &job_id, 955 trans_id_bitmap); 956 957 SMC_RET5(handle, status, trans_id_bitmap[0], trans_id_bitmap[1], 958 trans_id_bitmap[2], trans_id_bitmap[3]); 959 break; 960 } 961 962 case ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY: 963 { 964 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 965 GET_JOB_ID(x1), 966 MBOX_CMD_GET_DEVICEID, 967 NULL, 968 0U, 969 MBOX_CMD_FLAG_CASUAL, 970 sip_smc_ret_nbytes_cb, 971 (uint32_t *)x2, 972 2); 973 974 SMC_RET1(handle, status); 975 } 976 977 case ALTERA_SIP_SMC_ASYNC_GET_IDCODE: 978 { 979 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 980 GET_JOB_ID(x1), 981 MBOX_CMD_GET_IDCODE, 982 NULL, 983 0U, 984 MBOX_CMD_FLAG_CASUAL, 985 sip_smc_cmd_cb_ret3, 986 NULL, 987 0); 988 989 SMC_RET1(handle, status); 990 } 991 992 case ALTERA_SIP_SMC_ASYNC_QSPI_OPEN: 993 { 994 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 995 GET_JOB_ID(x1), 996 MBOX_CMD_QSPI_OPEN, 997 NULL, 998 0U, 999 MBOX_CMD_FLAG_CASUAL, 1000 sip_smc_cmd_cb_ret2, 1001 NULL, 1002 0U); 1003 1004 SMC_RET1(handle, status); 1005 } 1006 1007 case ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE: 1008 { 1009 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1010 GET_JOB_ID(x1), 1011 MBOX_CMD_QSPI_CLOSE, 1012 NULL, 1013 0U, 1014 MBOX_CMD_FLAG_CASUAL, 1015 sip_smc_cmd_cb_ret2, 1016 NULL, 1017 0U); 1018 1019 SMC_RET1(handle, status); 1020 } 1021 1022 case ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS: 1023 { 1024 uint32_t cmd_data = 0U; 1025 uint32_t chip_sel = (uint32_t)x2; 1026 uint32_t comb_addr_mode = (uint32_t)x3; 1027 uint32_t ext_dec_mode = (uint32_t)x4; 1028 1029 cmd_data = (chip_sel << MBOX_QSPI_SET_CS_OFFSET) | 1030 (comb_addr_mode << MBOX_QSPI_SET_CS_CA_OFFSET) | 1031 (ext_dec_mode << MBOX_QSPI_SET_CS_MODE_OFFSET); 1032 1033 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1034 GET_JOB_ID(x1), 1035 MBOX_CMD_QSPI_SET_CS, 1036 &cmd_data, 1037 1U, 1038 MBOX_CMD_FLAG_CASUAL, 1039 sip_smc_cmd_cb_ret2, 1040 NULL, 1041 0U); 1042 1043 SMC_RET1(handle, status); 1044 } 1045 1046 case ALTERA_SIP_SMC_ASYNC_QSPI_ERASE: 1047 { 1048 uint32_t qspi_addr = (uint32_t)x2; 1049 uint32_t qspi_nwords = (uint32_t)x3; 1050 1051 /* QSPI address offset to start erase, must be 4K aligned */ 1052 if (MBOX_IS_4K_ALIGNED(qspi_addr)) { 1053 ERROR("MBOX: 0x%x: QSPI address not 4K aligned\n", 1054 smc_fid); 1055 status = INTEL_SIP_SMC_STATUS_REJECTED; 1056 SMC_RET1(handle, status); 1057 } 1058 1059 /* Number of words to erase, multiples of 0x400 or 4K */ 1060 if (qspi_nwords % MBOX_QSPI_ERASE_SIZE_GRAN) { 1061 ERROR("MBOX: 0x%x: Given words not in multiples of 4K\n", 1062 smc_fid); 1063 status = INTEL_SIP_SMC_STATUS_REJECTED; 1064 SMC_RET1(handle, status); 1065 } 1066 1067 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1068 1069 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1070 GET_JOB_ID(x1), 1071 MBOX_CMD_QSPI_ERASE, 1072 cmd_data, 1073 sizeof(cmd_data) / MBOX_WORD_BYTE, 1074 MBOX_CMD_FLAG_CASUAL, 1075 sip_smc_cmd_cb_ret2, 1076 NULL, 1077 0U); 1078 1079 SMC_RET1(handle, status); 1080 } 1081 1082 case ALTERA_SIP_SMC_ASYNC_QSPI_WRITE: 1083 { 1084 uint32_t *qspi_payload = (uint32_t *)x2; 1085 uint32_t qspi_total_nwords = (((uint32_t)x3) / MBOX_WORD_BYTE); 1086 uint32_t qspi_addr = qspi_payload[0]; 1087 uint32_t qspi_nwords = qspi_payload[1]; 1088 1089 if (!MBOX_IS_WORD_ALIGNED(qspi_addr)) { 1090 ERROR("MBOX: 0x%x: Given address is not WORD aligned\n", 1091 smc_fid); 1092 status = INTEL_SIP_SMC_STATUS_REJECTED; 1093 SMC_RET1(handle, status); 1094 } 1095 1096 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1097 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1098 smc_fid); 1099 status = INTEL_SIP_SMC_STATUS_REJECTED; 1100 SMC_RET1(handle, status); 1101 } 1102 1103 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1104 GET_JOB_ID(x1), 1105 MBOX_CMD_QSPI_WRITE, 1106 qspi_payload, 1107 qspi_total_nwords, 1108 MBOX_CMD_FLAG_CASUAL, 1109 sip_smc_cmd_cb_ret2, 1110 NULL, 1111 0U); 1112 1113 SMC_RET1(handle, status); 1114 } 1115 1116 case ALTERA_SIP_SMC_ASYNC_QSPI_READ: 1117 { 1118 uint32_t qspi_addr = (uint32_t)x2; 1119 uint32_t qspi_nwords = (((uint32_t)x4) / MBOX_WORD_BYTE); 1120 1121 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1122 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1123 smc_fid); 1124 status = INTEL_SIP_SMC_STATUS_REJECTED; 1125 SMC_RET1(handle, status); 1126 } 1127 1128 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1129 1130 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1131 GET_JOB_ID(x1), 1132 MBOX_CMD_QSPI_READ, 1133 cmd_data, 1134 sizeof(cmd_data) / MBOX_WORD_BYTE, 1135 MBOX_CMD_FLAG_CASUAL, 1136 sip_smc_ret_nbytes_cb, 1137 (uint32_t *)x3, 1138 2); 1139 1140 SMC_RET1(handle, status); 1141 } 1142 1143 case ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO: 1144 { 1145 uint32_t *dst_addr = (uint32_t *)x2; 1146 1147 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1148 GET_JOB_ID(x1), 1149 MBOX_CMD_QSPI_GET_DEV_INFO, 1150 NULL, 1151 0U, 1152 MBOX_CMD_FLAG_CASUAL, 1153 sip_smc_ret_nbytes_cb, 1154 (uint32_t *)dst_addr, 1155 2); 1156 1157 SMC_RET1(handle, status); 1158 } 1159 1160 case ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT: 1161 case ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP: 1162 { 1163 uint32_t channel = (uint32_t)x2; 1164 uint32_t mbox_cmd = ((smc_fid == ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT) ? 1165 MBOX_HWMON_READVOLT : MBOX_HWMON_READTEMP); 1166 1167 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1168 GET_JOB_ID(x1), 1169 mbox_cmd, 1170 &channel, 1171 1U, 1172 MBOX_CMD_FLAG_CASUAL, 1173 sip_smc_cmd_cb_ret3, 1174 NULL, 1175 0); 1176 1177 SMC_RET1(handle, status); 1178 } 1179 1180 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT: 1181 { 1182 uint32_t session_id = (uint32_t)x2; 1183 uint32_t context_id = (uint32_t)x3; 1184 uint64_t ret_random_addr = (uint64_t)x4; 1185 uint32_t random_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1186 uint32_t crypto_header = 0U; 1187 1188 if ((random_len > (FCS_RANDOM_EXT_MAX_WORD_SIZE * MBOX_WORD_BYTE)) || 1189 (random_len == 0U) || 1190 (!is_size_4_bytes_aligned(random_len))) { 1191 ERROR("MBOX: 0x%x is rejected\n", smc_fid); 1192 status = INTEL_SIP_SMC_STATUS_REJECTED; 1193 SMC_RET1(handle, status); 1194 } 1195 1196 crypto_header = ((FCS_CS_FIELD_FLAG_INIT | FCS_CS_FIELD_FLAG_FINALIZE) << 1197 FCS_CS_FIELD_FLAG_OFFSET); 1198 fcs_rng_payload payload = {session_id, context_id, 1199 crypto_header, random_len}; 1200 1201 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1202 GET_JOB_ID(x1), 1203 MBOX_FCS_RANDOM_GEN, 1204 (uint32_t *)&payload, 1205 sizeof(payload) / MBOX_WORD_BYTE, 1206 MBOX_CMD_FLAG_CASUAL, 1207 sip_smc_ret_nbytes_cb, 1208 (uint32_t *)ret_random_addr, 1209 2); 1210 SMC_RET1(handle, status); 1211 } 1212 1213 case ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA: 1214 { 1215 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1216 GET_JOB_ID(x1), 1217 MBOX_FCS_GET_PROVISION, 1218 NULL, 1219 0U, 1220 MBOX_CMD_FLAG_CASUAL, 1221 sip_smc_ret_nbytes_cb, 1222 (uint32_t *)x2, 1223 2); 1224 SMC_RET1(handle, status); 1225 } 1226 1227 case ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH: 1228 { 1229 status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3, 1230 x4, &mbox_error); 1231 SMC_RET1(handle, status); 1232 } 1233 1234 case ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID: 1235 { 1236 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1237 GET_JOB_ID(x1), 1238 MBOX_CMD_GET_CHIPID, 1239 NULL, 1240 0U, 1241 MBOX_CMD_FLAG_CASUAL, 1242 sip_smc_get_chipid_cb, 1243 NULL, 1244 0); 1245 SMC_RET1(handle, status); 1246 } 1247 1248 case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT: 1249 { 1250 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3, 1251 (uint32_t *) &x4, &mbox_error); 1252 SMC_RET1(handle, status); 1253 } 1254 1255 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD: 1256 { 1257 status = intel_fcs_create_cert_on_reload(smc_fid, x1, 1258 x2, &mbox_error); 1259 SMC_RET1(handle, status); 1260 } 1261 1262 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT: 1263 { 1264 if (x4 == FCS_MODE_ENCRYPT) { 1265 status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3, 1266 x5, x6, x7, (uint32_t *) &x8, 1267 &mbox_error, x10, x11); 1268 } else if (x4 == FCS_MODE_DECRYPT) { 1269 status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3, 1270 x5, x6, x7, (uint32_t *) &x8, 1271 &mbox_error, x9, x10, x11); 1272 } else { 1273 ERROR("MBOX: 0x%x: Wrong crypto mode\n", smc_fid); 1274 status = INTEL_SIP_SMC_STATUS_REJECTED; 1275 } 1276 SMC_RET1(handle, status); 1277 } 1278 1279 case ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE: 1280 { 1281 status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error); 1282 SMC_RET1(handle, status); 1283 } 1284 1285 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION: 1286 { 1287 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1288 GET_JOB_ID(x1), 1289 MBOX_FCS_OPEN_CS_SESSION, 1290 NULL, 1291 0U, 1292 MBOX_CMD_FLAG_CASUAL, 1293 sip_smc_cmd_cb_ret3, 1294 NULL, 1295 0); 1296 SMC_RET1(handle, status); 1297 } 1298 1299 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION: 1300 { 1301 uint32_t session_id = (uint32_t)x2; 1302 1303 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1304 GET_JOB_ID(x1), 1305 MBOX_FCS_CLOSE_CS_SESSION, 1306 &session_id, 1307 1U, 1308 MBOX_CMD_FLAG_CASUAL, 1309 sip_smc_cmd_cb_ret2, 1310 NULL, 1311 0); 1312 SMC_RET1(handle, status); 1313 } 1314 1315 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY: 1316 { 1317 uint64_t key_addr = x2; 1318 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1319 1320 if ((key_len_words > FCS_CS_KEY_OBJ_MAX_WORD_SIZE) || 1321 (!is_address_in_ddr_range(key_addr, key_len_words * 4))) { 1322 ERROR("MBOX: 0x%x: Addr not in DDR range or key len exceeds\n", 1323 smc_fid); 1324 status = INTEL_SIP_SMC_STATUS_REJECTED; 1325 SMC_RET1(handle, status); 1326 } 1327 1328 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1329 GET_JOB_ID(x1), 1330 MBOX_FCS_IMPORT_CS_KEY, 1331 (uint32_t *)key_addr, 1332 key_len_words, 1333 MBOX_CMD_FLAG_CASUAL, 1334 sip_smc_cmd_cb_ret3, 1335 NULL, 1336 0); 1337 SMC_RET1(handle, status); 1338 } 1339 1340 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY: 1341 { 1342 uint64_t key_addr = x2; 1343 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1344 1345 if (!is_address_in_ddr_range(key_addr, key_len_words * 4)) { 1346 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1347 status = INTEL_SIP_SMC_STATUS_REJECTED; 1348 SMC_RET1(handle, status); 1349 } 1350 1351 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1352 GET_JOB_ID(x1), 1353 MBOX_FCS_CREATE_CS_KEY, 1354 (uint32_t *)key_addr, 1355 key_len_words, 1356 MBOX_CMD_FLAG_CASUAL, 1357 sip_smc_cmd_cb_ret3, 1358 NULL, 1359 0); 1360 SMC_RET1(handle, status); 1361 } 1362 1363 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY: 1364 { 1365 uint32_t session_id = (uint32_t)x2; 1366 uint32_t key_uid = (uint32_t)x3; 1367 uint64_t ret_key_addr = (uint64_t)x4; 1368 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1369 1370 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1371 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1372 status = INTEL_SIP_SMC_STATUS_REJECTED; 1373 SMC_RET1(handle, status); 1374 } 1375 1376 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1377 RESERVED_AS_ZERO, key_uid}; 1378 1379 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1380 GET_JOB_ID(x1), 1381 MBOX_FCS_EXPORT_CS_KEY, 1382 (uint32_t *)&payload, 1383 sizeof(payload) / MBOX_WORD_BYTE, 1384 MBOX_CMD_FLAG_CASUAL, 1385 sip_smc_ret_nbytes_cb, 1386 (uint32_t *)ret_key_addr, 1387 2); 1388 SMC_RET1(handle, status); 1389 } 1390 1391 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY: 1392 { 1393 uint32_t session_id = (uint32_t)x2; 1394 uint32_t key_uid = (uint32_t)x3; 1395 1396 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1397 RESERVED_AS_ZERO, key_uid}; 1398 1399 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1400 GET_JOB_ID(x1), 1401 MBOX_FCS_REMOVE_CS_KEY, 1402 (uint32_t *)&payload, 1403 sizeof(payload) / MBOX_WORD_BYTE, 1404 MBOX_CMD_FLAG_CASUAL, 1405 sip_smc_cmd_cb_ret3, 1406 NULL, 1407 0); 1408 SMC_RET1(handle, status); 1409 } 1410 1411 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO: 1412 { 1413 uint32_t session_id = (uint32_t)x2; 1414 uint32_t key_uid = (uint32_t)x3; 1415 uint64_t ret_key_addr = (uint64_t)x4; 1416 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1417 1418 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1419 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1420 status = INTEL_SIP_SMC_STATUS_REJECTED; 1421 SMC_RET1(handle, status); 1422 } 1423 1424 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1425 RESERVED_AS_ZERO, key_uid}; 1426 1427 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1428 GET_JOB_ID(x1), 1429 MBOX_FCS_GET_CS_KEY_INFO, 1430 (uint32_t *)&payload, 1431 sizeof(payload) / MBOX_WORD_BYTE, 1432 MBOX_CMD_FLAG_CASUAL, 1433 sip_smc_ret_nbytes_cb, 1434 (uint32_t *)ret_key_addr, 1435 2); 1436 SMC_RET1(handle, status); 1437 } 1438 1439 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT: 1440 { 1441 status = intel_fcs_aes_crypt_init(x2, x3, x4, x5, 1442 x6, &mbox_error); 1443 SMC_RET1(handle, status); 1444 } 1445 1446 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE: 1447 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE: 1448 { 1449 uint32_t job_id = 0U; 1450 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE) ? 1451 true : false; 1452 1453 status = intel_fcs_aes_crypt_update_finalize(smc_fid, x1, x2, 1454 x3, x4, x5, x6, x7, x8, is_final, 1455 &job_id, x9, x10); 1456 SMC_RET1(handle, status); 1457 } 1458 1459 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT: 1460 { 1461 status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6, 1462 &mbox_error); 1463 SMC_RET1(handle, status); 1464 } 1465 1466 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE: 1467 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE: 1468 { 1469 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE) ? 1470 true : false; 1471 1472 status = intel_fcs_get_digest_update_finalize(smc_fid, x1, x2, 1473 x3, x4, x5, x6, (uint32_t *) &x7, 1474 is_final, &mbox_error, x8); 1475 1476 SMC_RET1(handle, status); 1477 } 1478 1479 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT: 1480 { 1481 status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6, 1482 &mbox_error); 1483 SMC_RET1(handle, status); 1484 } 1485 1486 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE: 1487 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE: 1488 { 1489 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE) ? 1490 true : false; 1491 1492 status = intel_fcs_mac_verify_update_finalize(smc_fid, x1, x2, 1493 x3, x4, x5, x6, (uint32_t *) &x7, x8, 1494 is_final, &mbox_error, x9); 1495 SMC_RET1(handle, status); 1496 } 1497 1498 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT: 1499 { 1500 status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6, 1501 &mbox_error); 1502 SMC_RET1(handle, status); 1503 } 1504 1505 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1506 { 1507 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3, 1508 x4, x5, x6, (uint32_t *) &x7, 1509 &mbox_error); 1510 SMC_RET1(handle, status); 1511 } 1512 1513 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1514 { 1515 status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6, 1516 &mbox_error); 1517 SMC_RET1(handle, status); 1518 } 1519 1520 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1521 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1522 { 1523 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE) 1524 ? true : false; 1525 1526 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 1527 x1, x2, x3, x4, x5, x6, (uint32_t *) &x7, 1528 is_final, &mbox_error, x8); 1529 SMC_RET1(handle, status); 1530 } 1531 1532 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1533 { 1534 status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5, 1535 x6, &mbox_error); 1536 SMC_RET1(handle, status); 1537 } 1538 1539 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1540 { 1541 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, x1, 1542 x2, x3, x4, x5, x6, (uint32_t *) &x7, 1543 &mbox_error); 1544 SMC_RET1(handle, status); 1545 } 1546 1547 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1548 { 1549 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4, 1550 x5, x6, &mbox_error); 1551 SMC_RET1(handle, status); 1552 } 1553 1554 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1555 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1556 { 1557 bool is_final = (smc_fid == 1558 ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE) ? 1559 true : false; 1560 1561 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1562 smc_fid, x1, x2, x3, x4, x5, x6, 1563 (uint32_t *) &x7, x8, is_final, 1564 &mbox_error, x9); 1565 SMC_RET1(handle, status); 1566 } 1567 1568 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT: 1569 { 1570 status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6, 1571 &mbox_error); 1572 SMC_RET1(handle, status); 1573 } 1574 1575 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1576 { 1577 status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3, 1578 x4, (uint32_t *) &x5, &mbox_error); 1579 SMC_RET1(handle, status); 1580 } 1581 1582 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT: 1583 { 1584 status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6, 1585 &mbox_error); 1586 SMC_RET1(handle, status); 1587 } 1588 1589 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE: 1590 { 1591 uint32_t dest_size = (uint32_t)x7; 1592 1593 NOTICE("MBOX: %s, %d: x7 0x%x, dest_size 0x%x\n", 1594 __func__, __LINE__, (uint32_t)x7, dest_size); 1595 1596 status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3, 1597 x4, x5, x6, (uint32_t *) &dest_size, 1598 &mbox_error); 1599 SMC_RET1(handle, status); 1600 } 1601 1602 case ALTERA_SIP_SMC_ASYNC_MCTP_MSG: 1603 { 1604 uint32_t *src_addr = (uint32_t *)x2; 1605 uint32_t src_size = (uint32_t)x3; 1606 uint32_t *dst_addr = (uint32_t *)x4; 1607 1608 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1609 GET_JOB_ID(x1), 1610 MBOX_CMD_MCTP_MSG, 1611 src_addr, 1612 src_size / MBOX_WORD_BYTE, 1613 MBOX_CMD_FLAG_CASUAL, 1614 sip_smc_ret_nbytes_cb, 1615 dst_addr, 1616 2); 1617 1618 SMC_RET1(handle, status); 1619 } 1620 1621 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST: 1622 { 1623 status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6, 1624 x7); 1625 SMC_RET1(handle, status); 1626 } 1627 1628 default: 1629 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1630 cookie, handle, flags); 1631 } /* switch (smc_fid) */ 1632 } 1633 #endif 1634 1635 /* 1636 * This function is responsible for handling all SiP calls from the NS world 1637 */ 1638 1639 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 1640 u_register_t x1, 1641 u_register_t x2, 1642 u_register_t x3, 1643 u_register_t x4, 1644 void *cookie, 1645 void *handle, 1646 u_register_t flags) 1647 { 1648 uint32_t retval = 0, completed_addr[3]; 1649 uint32_t retval2 = 0; 1650 uint32_t mbox_error = 0; 1651 uint32_t err_states = 0; 1652 uint64_t retval64, rsu_respbuf[9]; 1653 uint32_t seu_respbuf[3]; 1654 int status = INTEL_SIP_SMC_STATUS_OK; 1655 int mbox_status; 1656 unsigned int len_in_resp; 1657 u_register_t x5, x6, x7; 1658 1659 switch (smc_fid) { 1660 case SIP_SVC_UID: 1661 /* Return UID to the caller */ 1662 SMC_UUID_RET(handle, intl_svc_uid); 1663 1664 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 1665 status = intel_mailbox_fpga_config_isdone(&err_states); 1666 SMC_RET4(handle, status, err_states, 0, 0); 1667 1668 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 1669 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1670 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 1671 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 1672 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 1673 1674 case INTEL_SIP_SMC_FPGA_CONFIG_START: 1675 status = intel_fpga_config_start(x1); 1676 SMC_RET4(handle, status, 0, 0, 0); 1677 1678 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 1679 status = intel_fpga_config_write(x1, x2); 1680 SMC_RET4(handle, status, 0, 0, 0); 1681 1682 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 1683 status = intel_fpga_config_completed_write(completed_addr, 1684 &retval, &rcv_id); 1685 switch (retval) { 1686 case 1: 1687 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1688 completed_addr[0], 0, 0); 1689 1690 case 2: 1691 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1692 completed_addr[0], 1693 completed_addr[1], 0); 1694 1695 case 3: 1696 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1697 completed_addr[0], 1698 completed_addr[1], 1699 completed_addr[2]); 1700 1701 case 0: 1702 SMC_RET4(handle, status, 0, 0, 0); 1703 1704 default: 1705 mailbox_clear_response(); 1706 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 1707 } 1708 1709 case INTEL_SIP_SMC_REG_READ: 1710 status = intel_secure_reg_read(x1, &retval); 1711 SMC_RET3(handle, status, retval, x1); 1712 1713 case INTEL_SIP_SMC_REG_WRITE: 1714 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 1715 SMC_RET3(handle, status, retval, x1); 1716 1717 case INTEL_SIP_SMC_REG_UPDATE: 1718 status = intel_secure_reg_update(x1, (uint32_t)x2, 1719 (uint32_t)x3, &retval); 1720 SMC_RET3(handle, status, retval, x1); 1721 1722 case INTEL_SIP_SMC_RSU_STATUS: 1723 status = intel_rsu_status(rsu_respbuf, 1724 ARRAY_SIZE(rsu_respbuf)); 1725 if (status) { 1726 SMC_RET1(handle, status); 1727 } else { 1728 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 1729 rsu_respbuf[2], rsu_respbuf[3]); 1730 } 1731 1732 case INTEL_SIP_SMC_RSU_UPDATE: 1733 status = intel_rsu_update(x1); 1734 SMC_RET1(handle, status); 1735 1736 case INTEL_SIP_SMC_RSU_NOTIFY: 1737 status = intel_rsu_notify(x1); 1738 SMC_RET1(handle, status); 1739 1740 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 1741 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 1742 ARRAY_SIZE(rsu_respbuf), &retval); 1743 if (status) { 1744 SMC_RET1(handle, status); 1745 } else { 1746 SMC_RET2(handle, status, retval); 1747 } 1748 1749 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 1750 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1751 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 1752 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 1753 1754 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 1755 status = intel_rsu_copy_dcmf_version(x1, x2); 1756 SMC_RET1(handle, status); 1757 1758 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO: 1759 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf, 1760 ARRAY_SIZE(rsu_respbuf)); 1761 if (status) { 1762 SMC_RET1(handle, status); 1763 } else { 1764 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1], 1765 rsu_respbuf[2], rsu_respbuf[3]); 1766 } 1767 1768 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 1769 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 1770 ((uint64_t)rsu_dcmf_stat[3] << 48) | 1771 ((uint64_t)rsu_dcmf_stat[2] << 32) | 1772 ((uint64_t)rsu_dcmf_stat[1] << 16) | 1773 rsu_dcmf_stat[0]); 1774 1775 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 1776 status = intel_rsu_copy_dcmf_status(x1); 1777 SMC_RET1(handle, status); 1778 1779 case INTEL_SIP_SMC_RSU_MAX_RETRY: 1780 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 1781 1782 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 1783 rsu_max_retry = x1; 1784 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 1785 1786 case INTEL_SIP_SMC_ECC_DBE: 1787 status = intel_ecc_dbe_notification(x1); 1788 SMC_RET1(handle, status); 1789 1790 case INTEL_SIP_SMC_SERVICE_COMPLETED: 1791 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 1792 &len_in_resp, &mbox_error); 1793 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 1794 1795 case INTEL_SIP_SMC_FIRMWARE_VERSION: 1796 status = intel_smc_fw_version(&retval); 1797 SMC_RET2(handle, status, retval); 1798 1799 case INTEL_SIP_SMC_MBOX_SEND_CMD: 1800 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1801 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1802 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 1803 &mbox_status, &len_in_resp); 1804 SMC_RET3(handle, status, mbox_status, len_in_resp); 1805 1806 case INTEL_SIP_SMC_GET_USERCODE: 1807 status = intel_smc_get_usercode(&retval); 1808 SMC_RET2(handle, status, retval); 1809 1810 case INTEL_SIP_SMC_FCS_CRYPTION: 1811 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1812 1813 if (x1 == FCS_MODE_DECRYPT) { 1814 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 1815 } else if (x1 == FCS_MODE_ENCRYPT) { 1816 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 1817 } else { 1818 status = INTEL_SIP_SMC_STATUS_REJECTED; 1819 } 1820 1821 SMC_RET3(handle, status, x4, x5); 1822 1823 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 1824 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1825 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1826 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1827 1828 if (x3 == FCS_MODE_DECRYPT) { 1829 status = intel_fcs_decryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 1830 (uint32_t *) &x7, &mbox_error, 0, 0, 0); 1831 } else if (x3 == FCS_MODE_ENCRYPT) { 1832 status = intel_fcs_encryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 1833 (uint32_t *) &x7, &mbox_error, 0, 0); 1834 } else { 1835 status = INTEL_SIP_SMC_STATUS_REJECTED; 1836 } 1837 1838 SMC_RET4(handle, status, mbox_error, x6, x7); 1839 1840 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 1841 status = intel_fcs_random_number_gen(x1, &retval64, 1842 &mbox_error); 1843 SMC_RET4(handle, status, mbox_error, x1, retval64); 1844 1845 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 1846 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 1847 &send_id); 1848 SMC_RET1(handle, status); 1849 1850 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 1851 status = intel_fcs_send_cert(smc_fid, 0, x1, x2, &send_id); 1852 SMC_RET1(handle, status); 1853 1854 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 1855 status = intel_fcs_get_provision_data(&send_id); 1856 SMC_RET1(handle, status); 1857 1858 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 1859 status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3, 1860 &mbox_error); 1861 SMC_RET2(handle, status, mbox_error); 1862 1863 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 1864 status = intel_hps_set_bridges(x1, x2); 1865 SMC_RET1(handle, status); 1866 1867 case INTEL_SIP_SMC_HWMON_READTEMP: 1868 status = intel_hwmon_readtemp(x1, &retval); 1869 SMC_RET2(handle, status, retval); 1870 1871 case INTEL_SIP_SMC_HWMON_READVOLT: 1872 status = intel_hwmon_readvolt(x1, &retval); 1873 SMC_RET2(handle, status, retval); 1874 1875 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 1876 status = intel_fcs_sigma_teardown(x1, &mbox_error); 1877 SMC_RET2(handle, status, mbox_error); 1878 1879 case INTEL_SIP_SMC_FCS_CHIP_ID: 1880 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 1881 SMC_RET4(handle, status, mbox_error, retval, retval2); 1882 1883 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 1884 status = intel_fcs_attestation_subkey(x1, x2, x3, 1885 (uint32_t *) &x4, &mbox_error); 1886 SMC_RET4(handle, status, mbox_error, x3, x4); 1887 1888 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 1889 status = intel_fcs_get_measurement(x1, x2, x3, 1890 (uint32_t *) &x4, &mbox_error); 1891 SMC_RET4(handle, status, mbox_error, x3, x4); 1892 1893 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 1894 status = intel_fcs_get_attestation_cert(smc_fid, 0, x1, x2, 1895 (uint32_t *) &x3, &mbox_error); 1896 SMC_RET4(handle, status, mbox_error, x2, x3); 1897 1898 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 1899 status = intel_fcs_create_cert_on_reload(smc_fid, 0, x1, &mbox_error); 1900 SMC_RET2(handle, status, mbox_error); 1901 1902 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 1903 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 1904 SMC_RET3(handle, status, mbox_error, retval); 1905 1906 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 1907 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 1908 SMC_RET2(handle, status, mbox_error); 1909 1910 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 1911 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 1912 SMC_RET1(handle, status); 1913 1914 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 1915 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 1916 (uint32_t *) &x4, &mbox_error); 1917 SMC_RET4(handle, status, mbox_error, x3, x4); 1918 1919 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 1920 status = intel_fcs_remove_crypto_service_key(x1, x2, 1921 &mbox_error); 1922 SMC_RET2(handle, status, mbox_error); 1923 1924 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 1925 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 1926 (uint32_t *) &x4, &mbox_error); 1927 SMC_RET4(handle, status, mbox_error, x3, x4); 1928 1929 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 1930 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1931 status = intel_fcs_get_digest_init(x1, x2, x3, 1932 x4, x5, &mbox_error); 1933 SMC_RET2(handle, status, mbox_error); 1934 1935 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 1936 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1937 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1938 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 1939 x3, x4, x5, (uint32_t *) &x6, false, 1940 &mbox_error, 0); 1941 SMC_RET4(handle, status, mbox_error, x5, x6); 1942 1943 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 1944 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1945 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1946 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 1947 x3, x4, x5, (uint32_t *) &x6, true, 1948 &mbox_error, 0); 1949 SMC_RET4(handle, status, mbox_error, x5, x6); 1950 1951 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 1952 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1953 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1954 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1955 x4, x5, (uint32_t *) &x6, false, 1956 &mbox_error, &send_id); 1957 SMC_RET4(handle, status, mbox_error, x5, x6); 1958 1959 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 1960 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1961 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1962 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1963 x4, x5, (uint32_t *) &x6, true, 1964 &mbox_error, &send_id); 1965 SMC_RET4(handle, status, mbox_error, x5, x6); 1966 1967 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 1968 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1969 status = intel_fcs_mac_verify_init(x1, x2, x3, 1970 x4, x5, &mbox_error); 1971 SMC_RET2(handle, status, mbox_error); 1972 1973 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 1974 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1975 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1976 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1977 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 1978 x3, x4, x5, (uint32_t *) &x6, x7, false, 1979 &mbox_error, 0); 1980 SMC_RET4(handle, status, mbox_error, x5, x6); 1981 1982 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 1983 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1984 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1985 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1986 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 1987 x3, x4, x5, (uint32_t *) &x6, x7, true, 1988 &mbox_error, 0); 1989 SMC_RET4(handle, status, mbox_error, x5, x6); 1990 1991 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 1992 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1993 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1994 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1995 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1996 x4, x5, (uint32_t *) &x6, x7, 1997 false, &mbox_error, &send_id); 1998 SMC_RET4(handle, status, mbox_error, x5, x6); 1999 2000 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 2001 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2002 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2003 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2004 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2005 x4, x5, (uint32_t *) &x6, x7, 2006 true, &mbox_error, &send_id); 2007 SMC_RET4(handle, status, mbox_error, x5, x6); 2008 2009 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 2010 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2011 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 2012 x4, x5, &mbox_error); 2013 SMC_RET2(handle, status, mbox_error); 2014 2015 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 2016 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2017 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2018 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2019 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2020 false, &mbox_error, 0); 2021 SMC_RET4(handle, status, mbox_error, x5, x6); 2022 2023 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 2024 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2025 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2026 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2027 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2028 true, &mbox_error, 0); 2029 SMC_RET4(handle, status, mbox_error, x5, x6); 2030 2031 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 2032 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2033 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2034 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2035 x2, x3, x4, x5, (uint32_t *) &x6, false, 2036 &mbox_error, &send_id); 2037 SMC_RET4(handle, status, mbox_error, x5, x6); 2038 2039 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 2040 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2041 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2042 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2043 x2, x3, x4, x5, (uint32_t *) &x6, true, 2044 &mbox_error, &send_id); 2045 SMC_RET4(handle, status, mbox_error, x5, x6); 2046 2047 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 2048 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2049 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 2050 x4, x5, &mbox_error); 2051 SMC_RET2(handle, status, mbox_error); 2052 2053 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 2054 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2055 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2056 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, 0, x1, x2, 2057 x3, x4, x5, (uint32_t *) &x6, 2058 &mbox_error); 2059 SMC_RET4(handle, status, mbox_error, x5, x6); 2060 2061 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 2062 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2063 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 2064 x4, x5, &mbox_error); 2065 SMC_RET2(handle, status, mbox_error); 2066 2067 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 2068 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2069 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2070 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, 0, x1, 2071 x2, x3, x4, x5, (uint32_t *) &x6, 2072 &mbox_error); 2073 SMC_RET4(handle, status, mbox_error, x5, x6); 2074 2075 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 2076 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2077 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 2078 x4, x5, &mbox_error); 2079 SMC_RET2(handle, status, mbox_error); 2080 2081 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 2082 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2083 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2084 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2085 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2086 smc_fid, 0, x1, x2, x3, x4, x5, 2087 (uint32_t *) &x6, x7, false, 2088 &mbox_error, 0); 2089 SMC_RET4(handle, status, mbox_error, x5, x6); 2090 2091 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 2092 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2093 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2094 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2095 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2096 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2097 x7, false, &mbox_error, &send_id); 2098 SMC_RET4(handle, status, mbox_error, x5, x6); 2099 2100 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 2101 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2102 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2103 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2104 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2105 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2106 x7, true, &mbox_error, &send_id); 2107 SMC_RET4(handle, status, mbox_error, x5, x6); 2108 2109 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 2110 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2111 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2112 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2113 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2114 smc_fid, 0, x1, x2, x3, x4, x5, 2115 (uint32_t *) &x6, x7, true, 2116 &mbox_error, 0); 2117 SMC_RET4(handle, status, mbox_error, x5, x6); 2118 2119 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 2120 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2121 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 2122 x4, x5, &mbox_error); 2123 SMC_RET2(handle, status, mbox_error); 2124 2125 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 2126 status = intel_fcs_ecdsa_get_pubkey_finalize( 2127 INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE, 0, 2128 x1, x2, x3, (uint32_t *) &x4, &mbox_error); 2129 SMC_RET4(handle, status, mbox_error, x3, x4); 2130 2131 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 2132 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2133 status = intel_fcs_ecdh_request_init(x1, x2, x3, 2134 x4, x5, &mbox_error); 2135 SMC_RET2(handle, status, mbox_error); 2136 2137 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 2138 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2139 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2140 status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3, 2141 x4, x5, (uint32_t *) &x6, &mbox_error); 2142 SMC_RET4(handle, status, mbox_error, x5, x6); 2143 2144 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 2145 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2146 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 2147 &mbox_error); 2148 SMC_RET2(handle, status, mbox_error); 2149 2150 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 2151 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2152 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2153 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2154 x3, x4, x5, x6, 0, false, &send_id, 0, 0); 2155 SMC_RET1(handle, status); 2156 2157 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 2158 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2159 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2160 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2161 x3, x4, x5, x6, 0, true, &send_id, 0, 0); 2162 SMC_RET1(handle, status); 2163 2164 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2165 case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG: 2166 status = intel_smmu_hps_remapper_config(x1); 2167 SMC_RET1(handle, status); 2168 #endif 2169 2170 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 2171 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 2172 &mbox_error); 2173 SMC_RET4(handle, status, mbox_error, x1, retval64); 2174 2175 case INTEL_SIP_SMC_SVC_VERSION: 2176 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2177 SIP_SVC_VERSION_MAJOR, 2178 SIP_SVC_VERSION_MINOR); 2179 2180 case INTEL_SIP_SMC_SEU_ERR_STATUS: 2181 status = intel_sdm_seu_err_read(seu_respbuf, 2182 ARRAY_SIZE(seu_respbuf)); 2183 if (status) { 2184 SMC_RET1(handle, status); 2185 } else { 2186 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 2187 } 2188 2189 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 2190 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 2191 SMC_RET1(handle, status); 2192 2193 case INTEL_SIP_SMC_ATF_BUILD_VER: 2194 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR, 2195 VERSION_MINOR, VERSION_PATCH); 2196 2197 default: 2198 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 2199 cookie, handle, flags); 2200 } 2201 } 2202 2203 uintptr_t sip_smc_handler(uint32_t smc_fid, 2204 u_register_t x1, 2205 u_register_t x2, 2206 u_register_t x3, 2207 u_register_t x4, 2208 void *cookie, 2209 void *handle, 2210 u_register_t flags) 2211 { 2212 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 2213 2214 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 2215 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 2216 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 2217 cookie, handle, flags); 2218 } 2219 #if SIP_SVC_V3 2220 else if ((cmd >= INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN) && 2221 (cmd <= INTEL_SIP_SMC_CMD_V3_RANGE_END)) { 2222 uintptr_t ret = sip_smc_handler_v3(smc_fid, x1, x2, x3, x4, 2223 cookie, handle, flags); 2224 return ret; 2225 } 2226 #endif 2227 else { 2228 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 2229 cookie, handle, flags); 2230 } 2231 } 2232 2233 DECLARE_RT_SVC( 2234 socfpga_sip_svc, 2235 OEN_SIP_START, 2236 OEN_SIP_END, 2237 SMC_TYPE_FAST, 2238 NULL, 2239 sip_smc_handler 2240 ); 2241 2242 DECLARE_RT_SVC( 2243 socfpga_sip_svc_std, 2244 OEN_SIP_START, 2245 OEN_SIP_END, 2246 SMC_TYPE_YIELD, 2247 NULL, 2248 sip_smc_handler 2249 ); 2250