1 /* 2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_SYSTEMMANAGER_H 8 #define SOCFPGA_SYSTEMMANAGER_H 9 10 #include "socfpga_plat_def.h" 11 12 /* System Manager Register Map */ 13 14 #define SOCFPGA_SYSMGR_SDMMC 0x28 15 16 /* Field Masking */ 17 #define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) 18 #define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4) 19 20 #define IDLE_DATA_LWSOC2FPGA BIT(4) 21 #define IDLE_DATA_SOC2FPGA BIT(0) 22 #define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) 23 24 #define SYSMGR_QSPI_REFCLK_MASK GENMASK(27, 0) 25 26 #define SYSMGR_ECC_OCRAM_MASK BIT(1) 27 #define SYSMGR_ECC_DDR0_MASK BIT(16) 28 #define SYSMGR_ECC_DDR1_MASK BIT(17) 29 30 /* Macros */ 31 32 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ 33 + (SOCFPGA_SYSMGR_##_reg)) 34 35 #endif /* SOCFPGA_SYSTEMMANAGER_H */ 36