1 /* 2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_SIP_SVC_H 8 #define SOCFPGA_SIP_SVC_H 9 10 11 /* SiP status response */ 12 #define INTEL_SIP_SMC_STATUS_OK 0 13 #define INTEL_SIP_SMC_STATUS_BUSY 0x1 14 #define INTEL_SIP_SMC_STATUS_REJECTED 0x2 15 #define INTEL_SIP_SMC_STATUS_NO_RESPONSE 0x3 16 #define INTEL_SIP_SMC_STATUS_ERROR 0x4 17 #define INTEL_SIP_SMC_RSU_ERROR 0x7 18 19 /* SiP mailbox error code */ 20 #define GENERIC_RESPONSE_ERROR 0x3FF 21 22 /* SiP V2 command code range */ 23 #define INTEL_SIP_SMC_CMD_MASK 0xFFFF 24 #define INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN 0x400 25 #define INTEL_SIP_SMC_CMD_V2_RANGE_END 0x4FF 26 27 /* SiP V2 protocol header */ 28 #define INTEL_SIP_SMC_HEADER_JOB_ID_MASK 0xF 29 #define INTEL_SIP_SMC_HEADER_JOB_ID_OFFSET 0U 30 #define INTEL_SIP_SMC_HEADER_CID_MASK 0xF 31 #define INTEL_SIP_SMC_HEADER_CID_OFFSET 4U 32 #define INTEL_SIP_SMC_HEADER_VERSION_MASK 0xF 33 #define INTEL_SIP_SMC_HEADER_VERSION_OFFSET 60U 34 35 /* SMC SiP service function identifier for version 1 */ 36 37 /* FPGA Reconfig */ 38 #define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001 39 #define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002 40 #define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003 41 #define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004 42 #define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005 43 44 /* FPGA Bitstream Flag */ 45 #define FLAG_PARTIAL_CONFIG BIT(0) 46 #define FLAG_AUTHENTICATION BIT(1) 47 #define CONFIG_TEST_FLAG(_flag, _type) (((flag) & FLAG_##_type) \ 48 == FLAG_##_type) 49 50 /* Secure Register Access */ 51 #define INTEL_SIP_SMC_REG_READ 0xC2000007 52 #define INTEL_SIP_SMC_REG_WRITE 0xC2000008 53 #define INTEL_SIP_SMC_REG_UPDATE 0xC2000009 54 55 /* Remote System Update */ 56 #define INTEL_SIP_SMC_RSU_STATUS 0xC200000B 57 #define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C 58 #define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E 59 #define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F 60 #define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010 61 #define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011 62 #define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012 63 #define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013 64 #define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014 65 #define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015 66 67 /* Hardware monitor */ 68 #define INTEL_SIP_SMC_HWMON_READTEMP 0xC2000020 69 #define INTEL_SIP_SMC_HWMON_READVOLT 0xC2000021 70 #define TEMP_CHANNEL_MAX (1 << 15) 71 #define VOLT_CHANNEL_MAX (1 << 15) 72 73 /* ECC */ 74 #define INTEL_SIP_SMC_ECC_DBE 0xC200000D 75 76 /* Generic Command */ 77 #define INTEL_SIP_SMC_SERVICE_COMPLETED 0xC200001E 78 #define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F 79 #define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032 80 #define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040 81 82 #define SERVICE_COMPLETED_MODE_ASYNC 0x00004F4E 83 84 /* Mailbox Command */ 85 #define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200003C 86 #define INTEL_SIP_SMC_GET_USERCODE 0xC200003D 87 88 /* FPGA Crypto Services */ 89 #define INTEL_SIP_SMC_FCS_RANDOM_NUMBER 0xC200005A 90 #define INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT 0x4200008F 91 #define INTEL_SIP_SMC_FCS_CRYPTION 0x4200005B 92 #define INTEL_SIP_SMC_FCS_CRYPTION_EXT 0xC2000090 93 #define INTEL_SIP_SMC_FCS_SERVICE_REQUEST 0x4200005C 94 #define INTEL_SIP_SMC_FCS_SEND_CERTIFICATE 0x4200005D 95 #define INTEL_SIP_SMC_FCS_GET_PROVISION_DATA 0x4200005E 96 #define INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH 0xC200005F 97 #define INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN 0xC2000064 98 #define INTEL_SIP_SMC_FCS_CHIP_ID 0xC2000065 99 #define INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY 0xC2000066 100 #define INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS 0xC2000067 101 #define INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT 0xC2000068 102 #define INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD 0xC2000069 103 #define INTEL_SIP_SMC_FCS_OPEN_CS_SESSION 0xC200006E 104 #define INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION 0xC200006F 105 #define INTEL_SIP_SMC_FCS_IMPORT_CS_KEY 0x42000070 106 #define INTEL_SIP_SMC_FCS_EXPORT_CS_KEY 0xC2000071 107 #define INTEL_SIP_SMC_FCS_REMOVE_CS_KEY 0xC2000072 108 #define INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO 0xC2000073 109 #define INTEL_SIP_SMC_FCS_AES_CRYPT_INIT 0xC2000074 110 #define INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE 0x42000075 111 #define INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE 0x42000076 112 #define INTEL_SIP_SMC_FCS_GET_DIGEST_INIT 0xC2000077 113 #define INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE 0xC2000078 114 #define INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE 0xC2000079 115 #define INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE 0x42000091 116 #define INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE 0x42000092 117 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT 0xC200007A 118 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE 0xC200007B 119 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE 0xC200007C 120 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE 0x42000093 121 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE 0x42000094 122 #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT 0xC200007D 123 #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE 0xC200007F 124 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT 0xC2000080 125 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE 0xC2000081 126 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE 0xC2000082 127 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE 0x42000095 128 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE 0x42000096 129 #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT 0xC2000083 130 #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE 0xC2000085 131 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT 0xC2000086 132 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE 0xC2000087 133 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE 0xC2000088 134 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE 0x42000097 135 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE 0x42000098 136 #define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT 0xC2000089 137 #define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE 0xC200008B 138 #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT 0xC200008C 139 #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE 0xC200008E 140 141 #define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF 142 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF 143 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U 144 #define INTEL_SIP_SMC_FCS_ECC_ALGO_MASK 0xF 145 146 /* ECC DBE */ 147 #define WARM_RESET_WFI_FLAG BIT(31) 148 #define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\ 149 SYSMGR_ECC_DDR0_MASK |\ 150 SYSMGR_ECC_DDR1_MASK) 151 152 /* Non-mailbox SMC Call */ 153 #define INTEL_SIP_SMC_SVC_VERSION 0xC2000200 154 155 /** 156 * SMC SiP service function identifier for version 2 157 * Command code from 0x400 ~ 0x4FF 158 */ 159 160 /* V2: Non-mailbox function identifier */ 161 #define INTEL_SIP_SMC_V2_GET_SVC_VERSION 0xC2000400 162 #define INTEL_SIP_SMC_V2_REG_READ 0xC2000401 163 #define INTEL_SIP_SMC_V2_REG_WRITE 0xC2000402 164 #define INTEL_SIP_SMC_V2_REG_UPDATE 0xC2000403 165 #define INTEL_SIP_SMC_V2_HPS_SET_BRIDGES 0xC2000404 166 167 /* V2: Mailbox function identifier */ 168 #define INTEL_SIP_SMC_V2_MAILBOX_SEND_COMMAND 0xC2000420 169 #define INTEL_SIP_SMC_V2_MAILBOX_POLL_RESPONSE 0xC2000421 170 171 /* SMC function IDs for SiP Service queries */ 172 #define SIP_SVC_CALL_COUNT 0x8200ff00 173 #define SIP_SVC_UID 0x8200ff01 174 #define SIP_SVC_VERSION 0x8200ff03 175 176 /* SiP Service Calls version numbers */ 177 /* 178 * Increase if there is any backward compatibility impact 179 */ 180 #define SIP_SVC_VERSION_MAJOR 2 181 /* 182 * Increase if there is new SMC function ID being added 183 */ 184 #define SIP_SVC_VERSION_MINOR 1 185 186 187 /* Structure Definitions */ 188 struct fpga_config_info { 189 uint32_t addr; 190 int size; 191 int size_written; 192 uint32_t write_requested; 193 int subblocks_sent; 194 int block_number; 195 }; 196 197 typedef enum { 198 NO_REQUEST = 0, 199 RECONFIGURATION, 200 BITSTREAM_AUTH 201 } config_type; 202 203 /* Function Definitions */ 204 bool is_size_4_bytes_aligned(uint32_t size); 205 bool is_address_in_ddr_range(uint64_t addr, uint64_t size); 206 207 /* ECC DBE */ 208 bool cold_reset_for_ecc_dbe(void); 209 uint32_t intel_ecc_dbe_notification(uint64_t dbe_value); 210 211 /* Secure register access */ 212 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval); 213 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 214 uint32_t *retval); 215 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 216 uint32_t val, uint32_t *retval); 217 218 /* Miscellaneous HPS services */ 219 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask); 220 221 /* SiP Service handler for version 2 */ 222 uintptr_t sip_smc_handler_v2(uint32_t smc_fid, 223 u_register_t x1, 224 u_register_t x2, 225 u_register_t x3, 226 u_register_t x4, 227 void *cookie, 228 void *handle, 229 u_register_t flags); 230 231 #endif /* SOCFPGA_SIP_SVC_H */ 232