1 /* 2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3 * Copyright (c) 2024, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SOCFPGA_SIP_SVC_H 9 #define SOCFPGA_SIP_SVC_H 10 11 12 /* SiP status response */ 13 #define INTEL_SIP_SMC_STATUS_OK 0 14 #define INTEL_SIP_SMC_STATUS_BUSY 0x1 15 #define INTEL_SIP_SMC_STATUS_REJECTED 0x2 16 #define INTEL_SIP_SMC_STATUS_NO_RESPONSE 0x3 17 #define INTEL_SIP_SMC_STATUS_ERROR 0x4 18 #define INTEL_SIP_SMC_RSU_ERROR 0x7 19 #define INTEL_SIP_SMC_SEU_ERR_READ_ERROR 0x8 20 21 /* SiP mailbox error code */ 22 #define GENERIC_RESPONSE_ERROR 0x3FF 23 24 /* SiP V2 command code range */ 25 #define INTEL_SIP_SMC_CMD_MASK 0xFFFF 26 #define INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN 0x400 27 #define INTEL_SIP_SMC_CMD_V2_RANGE_END 0x4FF 28 29 /* SiP V2 protocol header */ 30 #define INTEL_SIP_SMC_HEADER_JOB_ID_MASK 0xF 31 #define INTEL_SIP_SMC_HEADER_JOB_ID_OFFSET 0U 32 #define INTEL_SIP_SMC_HEADER_CID_MASK 0xF 33 #define INTEL_SIP_SMC_HEADER_CID_OFFSET 4U 34 #define INTEL_SIP_SMC_HEADER_VERSION_MASK 0xF 35 #define INTEL_SIP_SMC_HEADER_VERSION_OFFSET 60U 36 37 /* SMC SiP service function identifier for version 1 */ 38 39 /* FPGA Reconfig */ 40 #define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001 41 #define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002 42 #define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003 43 #define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004 44 #define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005 45 46 /* FPGA Bitstream Flag */ 47 #define FLAG_PARTIAL_CONFIG BIT(0) 48 #define FLAG_AUTHENTICATION BIT(1) 49 #define CONFIG_TEST_FLAG(_flag, _type) (((flag) & FLAG_##_type) \ 50 == FLAG_##_type) 51 52 /* Secure Register Access */ 53 #define INTEL_SIP_SMC_REG_READ 0xC2000007 54 #define INTEL_SIP_SMC_REG_WRITE 0xC2000008 55 #define INTEL_SIP_SMC_REG_UPDATE 0xC2000009 56 57 /* Remote System Update */ 58 #define INTEL_SIP_SMC_RSU_STATUS 0xC200000B 59 #define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C 60 #define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E 61 #define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F 62 #define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010 63 #define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011 64 #define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012 65 #define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013 66 #define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014 67 #define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015 68 #define INTEL_SIP_SMC_RSU_GET_DEVICE_INFO 0xC2000016 69 70 /* Hardware monitor */ 71 #define INTEL_SIP_SMC_HWMON_READTEMP 0xC2000020 72 #define INTEL_SIP_SMC_HWMON_READVOLT 0xC2000021 73 #define TEMP_CHANNEL_MAX (1 << 15) 74 #define VOLT_CHANNEL_MAX (1 << 15) 75 76 /* ECC */ 77 #define INTEL_SIP_SMC_ECC_DBE 0xC200000D 78 79 /* Generic Command */ 80 #define INTEL_SIP_SMC_SERVICE_COMPLETED 0xC200001E 81 #define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F 82 #define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032 83 #define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040 84 85 #define SERVICE_COMPLETED_MODE_ASYNC 0x00004F4E 86 87 /* Mailbox Command */ 88 #define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200003C 89 #define INTEL_SIP_SMC_GET_USERCODE 0xC200003D 90 91 /* FPGA Crypto Services */ 92 #define INTEL_SIP_SMC_FCS_RANDOM_NUMBER 0xC200005A 93 #define INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT 0x4200008F 94 #define INTEL_SIP_SMC_FCS_CRYPTION 0x4200005B 95 #define INTEL_SIP_SMC_FCS_CRYPTION_EXT 0xC2000090 96 #define INTEL_SIP_SMC_FCS_SERVICE_REQUEST 0x4200005C 97 #define INTEL_SIP_SMC_FCS_SEND_CERTIFICATE 0x4200005D 98 #define INTEL_SIP_SMC_FCS_GET_PROVISION_DATA 0x4200005E 99 #define INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH 0xC200005F 100 #define INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN 0xC2000064 101 #define INTEL_SIP_SMC_FCS_CHIP_ID 0xC2000065 102 #define INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY 0xC2000066 103 #define INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS 0xC2000067 104 #define INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT 0xC2000068 105 #define INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD 0xC2000069 106 #define INTEL_SIP_SMC_FCS_OPEN_CS_SESSION 0xC200006E 107 #define INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION 0xC200006F 108 #define INTEL_SIP_SMC_FCS_IMPORT_CS_KEY 0x42000070 109 #define INTEL_SIP_SMC_FCS_EXPORT_CS_KEY 0xC2000071 110 #define INTEL_SIP_SMC_FCS_REMOVE_CS_KEY 0xC2000072 111 #define INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO 0xC2000073 112 #define INTEL_SIP_SMC_FCS_AES_CRYPT_INIT 0xC2000074 113 #define INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE 0x42000075 114 #define INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE 0x42000076 115 #define INTEL_SIP_SMC_FCS_GET_DIGEST_INIT 0xC2000077 116 #define INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE 0xC2000078 117 #define INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE 0xC2000079 118 #define INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE 0x42000091 119 #define INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE 0x42000092 120 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT 0xC200007A 121 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE 0xC200007B 122 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE 0xC200007C 123 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE 0x42000093 124 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE 0x42000094 125 #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT 0xC200007D 126 #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE 0xC200007F 127 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT 0xC2000080 128 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE 0xC2000081 129 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE 0xC2000082 130 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE 0x42000095 131 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE 0x42000096 132 #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT 0xC2000083 133 #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE 0xC2000085 134 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT 0xC2000086 135 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE 0xC2000087 136 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE 0xC2000088 137 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE 0x42000097 138 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE 0x42000098 139 #define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT 0xC2000089 140 #define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE 0xC200008B 141 #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT 0xC200008C 142 #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE 0xC200008E 143 144 /* SEU ERR */ 145 #define INTEL_SIP_SMC_SEU_ERR_STATUS 0xC2000099 146 #define INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR 0xC200009A 147 148 #define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF 149 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF 150 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U 151 #define INTEL_SIP_SMC_FCS_ECC_ALGO_MASK 0xF 152 153 /* ECC DBE */ 154 #define WARM_RESET_WFI_FLAG BIT(31) 155 #define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\ 156 SYSMGR_ECC_DDR0_MASK |\ 157 SYSMGR_ECC_DDR1_MASK) 158 159 /* Non-mailbox SMC Call */ 160 #define INTEL_SIP_SMC_SVC_VERSION 0xC2000200 161 162 /** 163 * SMC SiP service function identifier for version 2 164 * Command code from 0x400 ~ 0x4FF 165 */ 166 167 /* V2: Non-mailbox function identifier */ 168 #define INTEL_SIP_SMC_V2_GET_SVC_VERSION 0xC2000400 169 #define INTEL_SIP_SMC_V2_REG_READ 0xC2000401 170 #define INTEL_SIP_SMC_V2_REG_WRITE 0xC2000402 171 #define INTEL_SIP_SMC_V2_REG_UPDATE 0xC2000403 172 #define INTEL_SIP_SMC_V2_HPS_SET_BRIDGES 0xC2000404 173 #define INTEL_SIP_SMC_V2_RSU_UPDATE_ADDR 0xC2000405 174 175 /* V2: Mailbox function identifier */ 176 #define INTEL_SIP_SMC_V2_MAILBOX_SEND_COMMAND 0xC2000420 177 #define INTEL_SIP_SMC_V2_MAILBOX_POLL_RESPONSE 0xC2000421 178 179 /* SMC function IDs for SiP Service queries */ 180 #define SIP_SVC_CALL_COUNT 0x8200ff00 181 #define SIP_SVC_UID 0x8200ff01 182 #define SIP_SVC_VERSION 0x8200ff03 183 184 /* SiP Service Calls version numbers */ 185 /* 186 * Increase if there is any backward compatibility impact 187 */ 188 #define SIP_SVC_VERSION_MAJOR 2 189 /* 190 * Increase if there is new SMC function ID being added 191 */ 192 #define SIP_SVC_VERSION_MINOR 2 193 194 195 /* Structure Definitions */ 196 struct fpga_config_info { 197 uint32_t addr; 198 int size; 199 int size_written; 200 uint32_t write_requested; 201 int subblocks_sent; 202 int block_number; 203 }; 204 205 typedef enum { 206 NO_REQUEST = 0, 207 RECONFIGURATION, 208 BITSTREAM_AUTH 209 } config_type; 210 211 /* Function Definitions */ 212 bool is_size_4_bytes_aligned(uint32_t size); 213 bool is_address_in_ddr_range(uint64_t addr, uint64_t size); 214 215 /* ECC DBE */ 216 bool cold_reset_for_ecc_dbe(void); 217 uint32_t intel_ecc_dbe_notification(uint64_t dbe_value); 218 219 /* Secure register access */ 220 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval); 221 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 222 uint32_t *retval); 223 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 224 uint32_t val, uint32_t *retval); 225 226 /* Set RSU update address*/ 227 uint32_t intel_rsu_update(uint64_t update_address); 228 229 /* Miscellaneous HPS services */ 230 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask); 231 232 /* SiP Service handler for version 2 */ 233 uintptr_t sip_smc_handler_v2(uint32_t smc_fid, 234 u_register_t x1, 235 u_register_t x2, 236 u_register_t x3, 237 u_register_t x4, 238 void *cookie, 239 void *handle, 240 u_register_t flags); 241 242 #endif /* SOCFPGA_SIP_SVC_H */ 243