xref: /rk3399_ARM-atf/plat/intel/soc/common/include/socfpga_sip_svc.h (revision 692541051b8cb0f435ae46c5d7351231ee292319)
1 /*
2  * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef SOCFPGA_SIP_SVC_H
8 #define SOCFPGA_SIP_SVC_H
9 
10 
11 /* SiP status response */
12 #define INTEL_SIP_SMC_STATUS_OK					0
13 #define INTEL_SIP_SMC_STATUS_BUSY				0x1
14 #define INTEL_SIP_SMC_STATUS_REJECTED				0x2
15 #define INTEL_SIP_SMC_STATUS_NO_RESPONSE			0x3
16 #define INTEL_SIP_SMC_STATUS_ERROR				0x4
17 #define INTEL_SIP_SMC_RSU_ERROR					0x7
18 
19 /* SiP mailbox error code */
20 #define GENERIC_RESPONSE_ERROR					0x3FF
21 
22 /* SMC SiP service function identifier */
23 
24 /* FPGA Reconfig */
25 #define INTEL_SIP_SMC_FPGA_CONFIG_START				0xC2000001
26 #define INTEL_SIP_SMC_FPGA_CONFIG_WRITE				0x42000002
27 #define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE		0xC2000003
28 #define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE			0xC2000004
29 #define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM			0xC2000005
30 
31 /* FPGA Bitstream Flag */
32 #define FLAG_PARTIAL_CONFIG					BIT(0)
33 #define FLAG_AUTHENTICATION					BIT(1)
34 #define CONFIG_TEST_FLAG(_flag, _type)				(((flag) & FLAG_##_type) \
35 								== FLAG_##_type)
36 
37 /* Secure Register Access */
38 #define INTEL_SIP_SMC_REG_READ				0xC2000007
39 #define INTEL_SIP_SMC_REG_WRITE				0xC2000008
40 #define INTEL_SIP_SMC_REG_UPDATE			0xC2000009
41 
42 /* Remote System Update */
43 #define INTEL_SIP_SMC_RSU_STATUS				0xC200000B
44 #define INTEL_SIP_SMC_RSU_UPDATE				0xC200000C
45 #define INTEL_SIP_SMC_RSU_NOTIFY				0xC200000E
46 #define INTEL_SIP_SMC_RSU_RETRY_COUNTER				0xC200000F
47 #define INTEL_SIP_SMC_RSU_DCMF_VERSION				0xC2000010
48 #define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION			0xC2000011
49 #define INTEL_SIP_SMC_RSU_MAX_RETRY				0xC2000012
50 #define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY			0xC2000013
51 #define INTEL_SIP_SMC_RSU_DCMF_STATUS				0xC2000014
52 #define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS			0xC2000015
53 
54 /* Hardware monitor */
55 #define INTEL_SIP_SMC_HWMON_READTEMP				0xC2000020
56 #define INTEL_SIP_SMC_HWMON_READVOLT				0xC2000021
57 #define TEMP_CHANNEL_MAX					(1 << 15)
58 #define VOLT_CHANNEL_MAX					(1 << 15)
59 
60 /* ECC */
61 #define INTEL_SIP_SMC_ECC_DBE					0xC200000D
62 
63 /* Generic Command */
64 #define INTEL_SIP_SMC_MBOX_SEND_CMD				0xC200001E
65 #define INTEL_SIP_SMC_FIRMWARE_VERSION				0xC200001F
66 #define INTEL_SIP_SMC_HPS_SET_BRIDGES				0xC2000032
67 #define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384			0xC2000040
68 
69 #define SERVICE_COMPLETED_MODE_ASYNC				0x00004F4E
70 
71 /* Mailbox Command */
72 #define INTEL_SIP_SMC_GET_USERCODE				0xC200003D
73 
74 /* FPGA Crypto Services */
75 #define INTEL_SIP_SMC_FCS_RANDOM_NUMBER				0xC200005A
76 #define INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT			0x4200008F
77 #define INTEL_SIP_SMC_FCS_CRYPTION				0x4200005B
78 #define INTEL_SIP_SMC_FCS_CRYPTION_EXT				0xC2000090
79 #define INTEL_SIP_SMC_FCS_SEND_CERTIFICATE			0x4200005D
80 #define INTEL_SIP_SMC_FCS_GET_PROVISION_DATA			0x4200005E
81 #define INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH			0xC200005F
82 #define INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN			0xC2000064
83 #define INTEL_SIP_SMC_FCS_CHIP_ID				0xC2000065
84 #define INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY			0xC2000066
85 #define INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS		0xC2000067
86 #define INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT			0xC2000068
87 #define INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD			0xC2000069
88 #define INTEL_SIP_SMC_FCS_OPEN_CS_SESSION			0xC200006E
89 #define INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION			0xC200006F
90 #define INTEL_SIP_SMC_FCS_IMPORT_CS_KEY				0x42000070
91 #define INTEL_SIP_SMC_FCS_EXPORT_CS_KEY				0xC2000071
92 #define INTEL_SIP_SMC_FCS_REMOVE_CS_KEY				0xC2000072
93 #define INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO			0xC2000073
94 #define INTEL_SIP_SMC_FCS_AES_CRYPT_INIT			0xC2000074
95 #define INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE			0x42000076
96 #define INTEL_SIP_SMC_FCS_GET_DIGEST_INIT			0xC2000077
97 #define INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE			0xC2000079
98 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT			0xC200007A
99 #define INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE			0xC200007C
100 #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT			0xC200007D
101 #define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE		0xC200007F
102 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT		0xC2000080
103 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE		0xC2000082
104 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT	0xC2000086
105 #define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE	0xC2000088
106 #define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT			0xC2000089
107 #define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE		0xC200008B
108 #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT			0xC200008C
109 #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE			0xC200008E
110 
111 #define INTEL_SIP_SMC_FCS_SHA_MODE_MASK				0xF
112 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK			0xF
113 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET			4U
114 #define INTEL_SIP_SMC_FCS_ECC_ALGO_MASK				0xF
115 
116 /* ECC DBE */
117 #define WARM_RESET_WFI_FLAG					BIT(31)
118 #define SYSMGR_ECC_DBE_COLD_RST_MASK				(SYSMGR_ECC_OCRAM_MASK |\
119 								SYSMGR_ECC_DDR0_MASK |\
120 								SYSMGR_ECC_DDR1_MASK)
121 
122 /* Non-mailbox SMC Call */
123 #define INTEL_SIP_SMC_SVC_VERSION				0xC2000200
124 
125 /* SMC function IDs for SiP Service queries */
126 #define SIP_SVC_CALL_COUNT					0x8200ff00
127 #define SIP_SVC_UID						0x8200ff01
128 #define SIP_SVC_VERSION						0x8200ff03
129 
130 /* SiP Service Calls version numbers */
131 #define SIP_SVC_VERSION_MAJOR					1
132 #define SIP_SVC_VERSION_MINOR					0
133 
134 
135 /* Structure Definitions */
136 struct fpga_config_info {
137 	uint32_t addr;
138 	int size;
139 	int size_written;
140 	uint32_t write_requested;
141 	int subblocks_sent;
142 	int block_number;
143 };
144 
145 /* Function Definitions */
146 bool is_size_4_bytes_aligned(uint32_t size);
147 bool is_address_in_ddr_range(uint64_t addr, uint64_t size);
148 
149 /* ECC DBE */
150 bool cold_reset_for_ecc_dbe(void);
151 uint32_t intel_ecc_dbe_notification(uint64_t dbe_value);
152 
153 /* Miscellaneous HPS services */
154 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask);
155 
156 #endif /* SOCFPGA_SIP_SVC_H */
157