1 /* 2 * Copyright (c) 2024, Intel Corporation. All rights reserved. 3 * Copyright (c) 2025, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SOCFPGA_ROS_H 9 #define SOCFPGA_ROS_H 10 11 #include <arch_helpers.h> 12 #include <lib/utils_def.h> 13 14 /** status response*/ 15 #define ROS_RET_OK (0x00U) 16 #define ROS_RET_INVALID (0x01U) 17 #define ROS_RET_NOT_RSU_MODE (0x02U) 18 #define ROS_QSPI_READ_ERROR (0x03U) 19 #define ROS_SPT_BAD_MAGIC_NUM (0x04U) 20 #define ROS_SPT_CRC_ERROR (0x05U) 21 #define ROS_IMAGE_INDEX_ERR (0x06U) 22 #define ROS_IMAGE_PARTNUM_OVFL (0x07U) 23 24 #define ADDR_64(h, l) (((((unsigned long)(h)) & 0xffffffff) << 32) | \ 25 (((unsigned long)(l)) & 0xffffffff)) 26 27 #define RSU_GET_SPT_RESP_SIZE (4U) 28 29 #define RSU_STATUS_RES_SIZE (9U) 30 31 #define SPT_MAGIC_NUMBER (0x57713427U) 32 #define SPT_VERSION (0U) 33 #define SPT_FLAG_RESERVED (1U) 34 #define SPT_FLAG_READONLY (2U) 35 36 #define SPT_MAX_PARTITIONS (127U) 37 #define SPT_PARTITION_NAME_LENGTH (16U) 38 #define SPT_RSVD_LENGTH (4U) 39 #define SPT_SIZE (4096U) 40 /*BOOT_INFO + FACTORY_IMAGE + SPT0 + SPT1 + CPB0 + CPB1 + FACTORY_IM.SSBL+ *APP* + *APP*.SSBL*/ 41 #define SPT_MIN_PARTITIONS (9U) 42 43 #define FACTORY_IMAGE "FACTORY_IMAGE" 44 #define FACTORY_SSBL "SSBL.FACTORY_IM" 45 #define SSBL_PREFIX "SSBL." 46 47 typedef struct { 48 const uint32_t magic_number; 49 const uint32_t version; 50 const uint32_t partitions; 51 uint32_t checksum; 52 const uint32_t __RSVD[SPT_RSVD_LENGTH]; 53 struct { 54 const char name[SPT_PARTITION_NAME_LENGTH]; 55 const uint64_t offset; 56 const uint32_t length; 57 const uint32_t flags; 58 } partition[SPT_MAX_PARTITIONS]; 59 } __packed __aligned(4) spt_table_t; 60 61 uint32_t ros_qspi_get_ssbl_offset(unsigned long *offset); 62 63 #endif /* SOCFPGA_ROS_H */ 64