1*3f7b1490SHadi Asyrafi /* 2*3f7b1490SHadi Asyrafi * Copyright (c) 2019, Intel Corporation. All rights reserved. 3*3f7b1490SHadi Asyrafi * 4*3f7b1490SHadi Asyrafi * SPDX-License-Identifier: BSD-3-Clause 5*3f7b1490SHadi Asyrafi */ 6*3f7b1490SHadi Asyrafi 7*3f7b1490SHadi Asyrafi #ifndef PLATFORM_PRIVATE_H 8*3f7b1490SHadi Asyrafi #define PLATFORM_PRIVATE_H 9*3f7b1490SHadi Asyrafi 10*3f7b1490SHadi Asyrafi /******************************************************************************* 11*3f7b1490SHadi Asyrafi * Function and variable prototypes 12*3f7b1490SHadi Asyrafi ******************************************************************************/ 13*3f7b1490SHadi Asyrafi void socfgpa_configure_mmu_el3(unsigned long total_base, 14*3f7b1490SHadi Asyrafi unsigned long total_size, 15*3f7b1490SHadi Asyrafi unsigned long ro_start, 16*3f7b1490SHadi Asyrafi unsigned long ro_limit, 17*3f7b1490SHadi Asyrafi unsigned long coh_start, 18*3f7b1490SHadi Asyrafi unsigned long coh_limit); 19*3f7b1490SHadi Asyrafi 20*3f7b1490SHadi Asyrafi 21*3f7b1490SHadi Asyrafi void socfpga_configure_mmu_el1(unsigned long total_base, 22*3f7b1490SHadi Asyrafi unsigned long total_size, 23*3f7b1490SHadi Asyrafi unsigned long ro_start, 24*3f7b1490SHadi Asyrafi unsigned long ro_limit, 25*3f7b1490SHadi Asyrafi unsigned long coh_start, 26*3f7b1490SHadi Asyrafi unsigned long coh_limit); 27*3f7b1490SHadi Asyrafi 28*3f7b1490SHadi Asyrafi void socfpga_delay_timer_init(void); 29*3f7b1490SHadi Asyrafi 30*3f7b1490SHadi Asyrafi void socfpga_gic_driver_init(void); 31*3f7b1490SHadi Asyrafi 32*3f7b1490SHadi Asyrafi uint32_t socfpga_get_spsr_for_bl32_entry(void); 33*3f7b1490SHadi Asyrafi 34*3f7b1490SHadi Asyrafi uint32_t socfpga_get_spsr_for_bl33_entry(void); 35*3f7b1490SHadi Asyrafi 36*3f7b1490SHadi Asyrafi unsigned long socfpga_get_ns_image_entrypoint(void); 37*3f7b1490SHadi Asyrafi 38*3f7b1490SHadi Asyrafi 39*3f7b1490SHadi Asyrafi #endif /* PLATFORM_PRIVATE_H */ 40