1 /* 2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_MBOX_H 8 #define SOCFPGA_MBOX_H 9 10 #include <lib/utils_def.h> 11 12 13 #define MBOX_OFFSET 0xffa30000 14 15 #define MBOX_ATF_CLIENT_ID 0x1U 16 #define MBOX_MAX_JOB_ID 0xFU 17 #define MBOX_MAX_IND_JOB_ID (MBOX_MAX_JOB_ID - 1U) 18 #define MBOX_JOB_ID MBOX_MAX_JOB_ID 19 20 21 /* Mailbox Shared Memory Register Map */ 22 #define MBOX_CIN 0x00 23 #define MBOX_ROUT 0x04 24 #define MBOX_URG 0x08 25 #define MBOX_INT 0x0C 26 #define MBOX_COUT 0x20 27 #define MBOX_RIN 0x24 28 #define MBOX_STATUS 0x2C 29 #define MBOX_CMD_BUFFER 0x40 30 #define MBOX_RESP_BUFFER 0xC0 31 32 /* Mailbox SDM doorbell */ 33 #define MBOX_DOORBELL_TO_SDM 0x400 34 #define MBOX_DOORBELL_FROM_SDM 0x480 35 36 37 /* Mailbox commands */ 38 39 #define MBOX_CMD_NOOP 0x00 40 #define MBOX_CMD_SYNC 0x01 41 #define MBOX_CMD_RESTART 0x02 42 #define MBOX_CMD_CANCEL 0x03 43 #define MBOX_CMD_GET_IDCODE 0x10 44 #define MBOX_CMD_REBOOT_HPS 0x47 45 46 /* Reconfiguration Commands */ 47 #define MBOX_CONFIG_STATUS 0x04 48 #define MBOX_RECONFIG 0x06 49 #define MBOX_RECONFIG_DATA 0x08 50 #define MBOX_RECONFIG_STATUS 0x09 51 52 /* QSPI Commands */ 53 #define MBOX_CMD_QSPI_OPEN 0x32 54 #define MBOX_CMD_QSPI_CLOSE 0x33 55 #define MBOX_CMD_QSPI_SET_CS 0x34 56 #define MBOX_CMD_QSPI_DIRECT 0x3B 57 58 /* RSU Commands */ 59 #define MBOX_GET_SUBPARTITION_TABLE 0x5A 60 #define MBOX_RSU_STATUS 0x5B 61 #define MBOX_RSU_UPDATE 0x5C 62 #define MBOX_HPS_STAGE_NOTIFY 0x5D 63 64 65 /* Mailbox Definitions */ 66 67 #define CMD_DIRECT 0 68 #define CMD_INDIRECT 1 69 #define CMD_CASUAL 0 70 #define CMD_URGENT 1 71 72 #define MBOX_WORD_BYTE 4U 73 #define MBOX_RESP_BUFFER_SIZE 16 74 #define MBOX_CMD_BUFFER_SIZE 32 75 76 /* Execution states for HPS_STAGE_NOTIFY */ 77 #define HPS_EXECUTION_STATE_FSBL 0 78 #define HPS_EXECUTION_STATE_SSBL 1 79 #define HPS_EXECUTION_STATE_OS 2 80 81 /* Status Response */ 82 #define MBOX_RET_OK 0 83 #define MBOX_RET_ERROR -1 84 #define MBOX_NO_RESPONSE -2 85 #define MBOX_WRONG_ID -3 86 #define MBOX_BUFFER_FULL -4 87 #define MBOX_TIMEOUT -2047 88 89 /* Reconfig Status Response */ 90 #define RECONFIG_STATUS_STATE 0 91 #define RECONFIG_STATUS_PIN_STATUS 2 92 #define RECONFIG_STATUS_SOFTFUNC_STATUS 3 93 #define PIN_STATUS_NSTATUS (U(1) << 31) 94 #define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) 95 #define SOFTFUNC_STATUS_INIT_DONE (1 << 1) 96 #define SOFTFUNC_STATUS_CONF_DONE (1 << 0) 97 #define MBOX_CFGSTAT_STATE_IDLE 0x00000000 98 #define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 99 #define MBOX_CFGSTAT_STATE_FAILACK 0x08000000 100 #define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001 101 #define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002 102 #define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003 103 #define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004 104 #define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005 105 #define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006 106 #define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007 107 #define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008 108 109 110 /* Mailbox Macros */ 111 112 #define MBOX_ENTRY_TO_ADDR(_buf, ptr) (MBOX_OFFSET + (MBOX_##_buf##_BUFFER) \ 113 + MBOX_WORD_BYTE * (ptr)) 114 115 /* Mailbox interrupt flags and masks */ 116 #define MBOX_INT_FLAG_COE 0x1 117 #define MBOX_INT_FLAG_RIE 0x2 118 #define MBOX_INT_FLAG_UAE 0x100 119 #define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3) 120 #define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8))) 121 122 /* Mailbox response and status */ 123 #define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff) 124 #define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12) 125 #define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28) 126 #define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24) 127 #define MBOX_STATUS_UA_MASK (1<<8) 128 129 /* Mailbox command and response */ 130 #define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) 131 #define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) 132 #define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) 133 #define MBOX_INDIRECT(val) ((val) << 11) 134 #define MBOX_CMD_MASK(header) ((header) & 0x7ff) 135 136 /* RSU Macros */ 137 #define RSU_VERSION_ACMF BIT(8) 138 #define RSU_VERSION_ACMF_MASK 0xff00 139 140 141 /* Mailbox Function Definitions */ 142 143 void mailbox_set_int(uint32_t interrupt_input); 144 int mailbox_init(void); 145 void mailbox_set_qspi_close(void); 146 void mailbox_hps_qspi_enable(void); 147 148 int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args, 149 unsigned int len, uint32_t urgent, uint32_t *response, 150 unsigned int *resp_len); 151 int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args, 152 unsigned int len, unsigned int indirect); 153 int mailbox_read_response(uint32_t *job_id, uint32_t *response, 154 unsigned int *resp_len); 155 int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, 156 unsigned int *resp_len); 157 158 void mailbox_reset_cold(void); 159 void mailbox_clear_response(void); 160 161 int intel_mailbox_get_config_status(uint32_t cmd, bool init_done); 162 int intel_mailbox_is_fpga_not_ready(void); 163 164 int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len); 165 int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len); 166 int mailbox_rsu_update(uint32_t *flash_offset); 167 int mailbox_hps_stage_notify(uint32_t execution_stage); 168 169 #endif /* SOCFPGA_MBOX_H */ 170