1 /* 2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3 * Copyright (c) 2024, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SOCFPGA_MBOX_H 9 #define SOCFPGA_MBOX_H 10 11 #include <lib/utils_def.h> 12 13 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 14 #define MBOX_OFFSET 0x10a30000 15 #else 16 #define MBOX_OFFSET 0xffa30000 17 #endif 18 19 #define MBOX_ATF_CLIENT_ID 0x1U 20 #define MBOX_MAX_JOB_ID 0xFU 21 #define MBOX_MAX_IND_JOB_ID (MBOX_MAX_JOB_ID - 1U) 22 #define MBOX_JOB_ID MBOX_MAX_JOB_ID 23 #define MBOX_TEST_BIT BIT(31) 24 25 /* Mailbox Shared Memory Register Map */ 26 #define MBOX_CIN 0x00 27 #define MBOX_ROUT 0x04 28 #define MBOX_URG 0x08 29 #define MBOX_INT 0x0C 30 #define MBOX_COUT 0x20 31 #define MBOX_RIN 0x24 32 #define MBOX_STATUS 0x2C 33 #define MBOX_CMD_BUFFER 0x40 34 #define MBOX_RESP_BUFFER 0xC0 35 36 /* Mailbox SDM doorbell */ 37 #define MBOX_DOORBELL_TO_SDM 0x400 38 #define MBOX_DOORBELL_FROM_SDM 0x480 39 40 41 /* Mailbox commands */ 42 43 #define MBOX_CMD_NOOP 0x00 44 #define MBOX_CMD_SYNC 0x01 45 #define MBOX_CMD_RESTART 0x02 46 #define MBOX_CMD_CANCEL 0x03 47 #define MBOX_CMD_VAB_SRC_CERT 0x0B 48 #define MBOX_CMD_GET_IDCODE 0x10 49 #define MBOX_CMD_GET_USERCODE 0x13 50 #define MBOX_CMD_GET_CHIPID 0x12 51 #define MBOX_CMD_FPGA_CONFIG_COMP 0x45 52 #define MBOX_CMD_REBOOT_HPS 0x47 53 54 /* Reconfiguration Commands */ 55 #define MBOX_CONFIG_STATUS 0x04 56 #define MBOX_RECONFIG 0x06 57 #define MBOX_RECONFIG_DATA 0x08 58 #define MBOX_RECONFIG_STATUS 0x09 59 60 /* HWMON Commands */ 61 #define MBOX_HWMON_READVOLT 0x18 62 #define MBOX_HWMON_READTEMP 0x19 63 64 65 /* QSPI Commands */ 66 #define MBOX_CMD_QSPI_OPEN 0x32 67 #define MBOX_CMD_QSPI_CLOSE 0x33 68 #define MBOX_CMD_QSPI_SET_CS 0x34 69 #define MBOX_CMD_QSPI_DIRECT 0x3B 70 71 /* SEU Commands */ 72 #define MBOX_CMD_SEU_ERR_READ 0x3C 73 #define MBOX_CMD_SAFE_INJECT_SEU_ERR 0x41 74 75 /* RSU Commands */ 76 #define MBOX_GET_SUBPARTITION_TABLE 0x5A 77 #define MBOX_RSU_STATUS 0x5B 78 #define MBOX_RSU_UPDATE 0x5C 79 #define MBOX_HPS_STAGE_NOTIFY 0x5D 80 #define MBOX_RSU_GET_DEVICE_INFO 0x74 81 82 /* FCS Command */ 83 #define MBOX_FCS_GET_PROVISION 0x7B 84 #define MBOX_FCS_CNTR_SET_PREAUTH 0x7C 85 #define MBOX_FCS_ENCRYPT_REQ 0x7E 86 #define MBOX_FCS_DECRYPT_REQ 0x7F 87 #define MBOX_FCS_RANDOM_GEN 0x80 88 #define MBOX_FCS_AES_CRYPT_REQ 0x81 89 #define MBOX_FCS_GET_DIGEST_REQ 0x82 90 #define MBOX_FCS_MAC_VERIFY_REQ 0x83 91 #define MBOX_FCS_ECDSA_HASH_SIGN_REQ 0x84 92 #define MBOX_FCS_ECDSA_SHA2_DATA_SIGN_REQ 0x85 93 #define MBOX_FCS_ECDSA_HASH_SIG_VERIFY 0x86 94 #define MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY 0x87 95 #define MBOX_FCS_ECDSA_GET_PUBKEY 0x88 96 #define MBOX_FCS_ECDH_REQUEST 0x89 97 #define MBOX_FCS_OPEN_CS_SESSION 0xA0 98 #define MBOX_FCS_CLOSE_CS_SESSION 0xA1 99 #define MBOX_FCS_IMPORT_CS_KEY 0xA5 100 #define MBOX_FCS_EXPORT_CS_KEY 0xA6 101 #define MBOX_FCS_REMOVE_CS_KEY 0xA7 102 #define MBOX_FCS_GET_CS_KEY_INFO 0xA8 103 104 /* PSG SIGMA Commands */ 105 #define MBOX_PSG_SIGMA_TEARDOWN 0xD5 106 107 /* Attestation Commands */ 108 #define MBOX_CREATE_CERT_ON_RELOAD 0x180 109 #define MBOX_GET_ATTESTATION_CERT 0x181 110 #define MBOX_ATTESTATION_SUBKEY 0x182 111 #define MBOX_GET_MEASUREMENT 0x183 112 113 /* Miscellaneous commands */ 114 #define MBOX_GET_ROM_PATCH_SHA384 0x1B0 115 116 /* Mailbox Definitions */ 117 118 #define CMD_DIRECT 0 119 #define CMD_INDIRECT 1 120 #define CMD_CASUAL 0 121 #define CMD_URGENT 1 122 123 #define MBOX_WORD_BYTE 4U 124 #define MBOX_RESP_BUFFER_SIZE 16 125 #define MBOX_CMD_BUFFER_SIZE 32 126 #define MBOX_INC_HEADER_MAX_WORD_SIZE 1024U 127 128 /* Execution states for HPS_STAGE_NOTIFY */ 129 #define HPS_EXECUTION_STATE_FSBL 0 130 #define HPS_EXECUTION_STATE_SSBL 1 131 #define HPS_EXECUTION_STATE_OS 2 132 133 /* Status Response */ 134 #define MBOX_RET_OK 0 135 #define MBOX_RET_ERROR -1 136 #define MBOX_NO_RESPONSE -2 137 #define MBOX_WRONG_ID -3 138 #define MBOX_BUFFER_FULL -4 139 #define MBOX_BUSY -5 140 #define MBOX_TIMEOUT -2047 141 142 /* Key Status */ 143 #define MBOX_RET_SDOS_DECRYPTION_ERROR_102 -258 144 #define MBOX_RET_SDOS_DECRYPTION_ERROR_103 -259 145 146 /* Reconfig Status Response */ 147 #define RECONFIG_STATUS_STATE 0 148 #define RECONFIG_STATUS_PIN_STATUS 2 149 #define RECONFIG_STATUS_SOFTFUNC_STATUS 3 150 #define PIN_STATUS_NSTATUS (U(1) << 31) 151 #define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) 152 #define SOFTFUNC_STATUS_INIT_DONE (1 << 1) 153 #define SOFTFUNC_STATUS_CONF_DONE (1 << 0) 154 #define MBOX_CFGSTAT_STATE_IDLE 0x00000000 155 #define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 156 #define MBOX_CFGSTAT_VAB_BS_PREAUTH 0x20000000 157 #define MBOX_CFGSTAT_STATE_FAILACK 0x08000000 158 #define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001 159 #define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002 160 #define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003 161 #define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004 162 #define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005 163 #define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006 164 #define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007 165 #define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008 166 167 168 /* Mailbox Macros */ 169 170 #define MBOX_ENTRY_TO_ADDR(_buf, ptr) (MBOX_OFFSET + (MBOX_##_buf##_BUFFER) \ 171 + MBOX_WORD_BYTE * (ptr)) 172 173 /* Mailbox interrupt flags and masks */ 174 #define MBOX_INT_FLAG_COE 0x1 175 #define MBOX_INT_FLAG_RIE 0x2 176 #define MBOX_INT_FLAG_UAE 0x100 177 #define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3) 178 #define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8))) 179 180 /* Mailbox response and status */ 181 #define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x000007ff) 182 #define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12) 183 #define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28) 184 #define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24) 185 #define MBOX_STATUS_UA_MASK (1<<8) 186 187 /* Mailbox command and response */ 188 #define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) 189 #define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) 190 #define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) 191 #define MBOX_INDIRECT(val) ((val) << 11) 192 #define MBOX_CMD_MASK(header) ((header) & 0x7ff) 193 194 /* Mailbox payload */ 195 #define MBOX_DATA_MAX_LEN 0x3ff 196 #define MBOX_PAYLOAD_FLAG_BUSY BIT(0) 197 198 /* RSU Macros */ 199 #define RSU_VERSION_ACMF BIT(8) 200 #define RSU_VERSION_ACMF_MASK 0xff00 201 202 /* Config Status Macros */ 203 #define CONFIG_STATUS_WORD_SIZE 16U 204 #define CONFIG_STATUS_FW_VER_OFFSET 1 205 #define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF 206 207 /* Data structure */ 208 209 typedef struct mailbox_payload { 210 uint32_t header; 211 uint32_t data[MBOX_DATA_MAX_LEN]; 212 } mailbox_payload_t; 213 214 typedef struct mailbox_container { 215 uint32_t flag; 216 uint32_t index; 217 mailbox_payload_t *payload; 218 } mailbox_container_t; 219 220 /* Mailbox Function Definitions */ 221 222 void mailbox_set_int(uint32_t interrupt_input); 223 int mailbox_init(void); 224 void mailbox_set_qspi_close(void); 225 void mailbox_hps_qspi_enable(void); 226 227 int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args, 228 unsigned int len, uint32_t urgent, uint32_t *response, 229 unsigned int *resp_len); 230 int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args, 231 unsigned int len, unsigned int indirect); 232 int mailbox_send_cmd_async_ext(uint32_t header_cmd, uint32_t *args, 233 unsigned int len); 234 int mailbox_read_response(uint32_t *job_id, uint32_t *response, 235 unsigned int *resp_len); 236 int mailbox_read_response_async(uint32_t *job_id, uint32_t *header, 237 uint32_t *response, unsigned int *resp_len, 238 uint8_t ignore_client_id); 239 int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, 240 unsigned int *resp_len); 241 242 void mailbox_reset_cold(void); 243 void mailbox_reset_warm(uint32_t reset_type); 244 void mailbox_clear_response(void); 245 246 int intel_mailbox_get_config_status(uint32_t cmd, bool init_done, 247 uint32_t *err_states); 248 int intel_mailbox_is_fpga_not_ready(void); 249 250 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 251 void intel_smmu_hps_remapper_init(uint64_t *mem); 252 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass); 253 #endif 254 255 int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len); 256 int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len); 257 int mailbox_rsu_get_device_info(uint32_t *resp_buf, uint32_t resp_buf_len); 258 int mailbox_rsu_update(uint32_t *flash_offset); 259 int mailbox_hps_stage_notify(uint32_t execution_stage); 260 int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf); 261 int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf); 262 int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len); 263 int mailbox_safe_inject_seu_err(uint32_t *arg, unsigned int len); 264 265 int mailbox_send_fpga_config_comp(void); 266 267 #endif /* SOCFPGA_MBOX_H */ 268