1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_FCS_H 8 #define SOCFPGA_FCS_H 9 10 /* FCS Definitions */ 11 12 #define FCS_RANDOM_WORD_SIZE 8U 13 #define FCS_PROV_DATA_WORD_SIZE 44U 14 #define FCS_SHA384_WORD_SIZE 12U 15 16 #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) 17 #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) 18 #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) 19 20 #define FCS_CRYPTION_DATA_0 0x10100 21 22 /* FCS Payload Structure */ 23 24 typedef struct fcs_crypt_payload_t { 25 uint32_t first_word; 26 uint32_t src_addr; 27 uint32_t src_size; 28 uint32_t dst_addr; 29 uint32_t dst_size; 30 } fcs_crypt_payload; 31 32 /* Functions Definitions */ 33 34 uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, 35 uint32_t *mbox_error); 36 uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size, 37 uint32_t *send_id); 38 uint32_t intel_fcs_get_provision_data(uint32_t *send_id); 39 uint32_t intel_fcs_cryption(uint32_t mode, uint32_t src_addr, 40 uint32_t src_size, uint32_t dst_addr, 41 uint32_t dst_size, uint32_t *send_id); 42 43 uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, 44 uint32_t *mbox_error); 45 46 #endif /* SOCFPGA_FCS_H */ 47