1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_FCS_H 8 #define SOCFPGA_FCS_H 9 10 /* FCS Definitions */ 11 12 #define FCS_RANDOM_WORD_SIZE 8U 13 #define FCS_PROV_DATA_WORD_SIZE 44U 14 #define FCS_SHA384_WORD_SIZE 12U 15 16 #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) 17 #define FCS_RANDOM_EXT_MAX_WORD_SIZE 1020U 18 #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) 19 #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) 20 21 #define FCS_RANDOM_EXT_OFFSET 3 22 23 #define FCS_MODE_DECRYPT 0x0 24 #define FCS_MODE_ENCRYPT 0x1 25 #define FCS_ENCRYPTION_DATA_0 0x10100 26 #define FCS_DECRYPTION_DATA_0 0x10102 27 #define FCS_OWNER_ID_OFFSET 0xC 28 #define FCS_CRYPTION_CRYPTO_HEADER 0x07000000 29 #define FCS_CRYPTION_RESP_WORD_SIZE 4U 30 #define FCS_CRYPTION_RESP_SIZE_OFFSET 3U 31 32 #define PSGSIGMA_TEARDOWN_MAGIC 0xB852E2A4 33 #define PSGSIGMA_SESSION_ID_ONE 0x1 34 #define PSGSIGMA_UNKNOWN_SESSION 0xFFFFFFFF 35 36 #define RESERVED_AS_ZERO 0x0 37 /* FCS Single cert */ 38 39 #define FCS_BIG_CNTR_SEL 0x1 40 41 #define FCS_SVN_CNTR_0_SEL 0x2 42 #define FCS_SVN_CNTR_1_SEL 0x3 43 #define FCS_SVN_CNTR_2_SEL 0x4 44 #define FCS_SVN_CNTR_3_SEL 0x5 45 46 #define FCS_BIG_CNTR_VAL_MAX 495U 47 #define FCS_SVN_CNTR_VAL_MAX 64U 48 49 /* FCS Attestation Cert Request Parameter */ 50 51 #define FCS_ALIAS_CERT 0x01 52 #define FCS_DEV_ID_SELF_SIGN_CERT 0x02 53 #define FCS_DEV_ID_ENROLL_CERT 0x04 54 #define FCS_ENROLL_SELF_SIGN_CERT 0x08 55 #define FCS_PLAT_KEY_CERT 0x10 56 57 /* FCS Crypto Service */ 58 59 #define FCS_CS_KEY_OBJ_MAX_WORD_SIZE 88U 60 #define FCS_CS_KEY_INFO_MAX_WORD_SIZE 36U 61 #define FCS_CS_KEY_RESP_STATUS_MASK 0xFF 62 #define FCS_CS_KEY_RESP_STATUS_OFFSET 16U 63 64 #define FCS_CS_FIELD_SIZE_MASK 0xFFFF 65 #define FCS_CS_FIELD_FLAG_OFFSET 24 66 #define FCS_CS_FIELD_FLAG_INIT BIT(0) 67 #define FCS_CS_FIELD_FLAG_UPDATE BIT(1) 68 #define FCS_CS_FIELD_FLAG_FINALIZE BIT(2) 69 70 #define FCS_AES_MAX_DATA_SIZE 0x10000000 /* 256 MB */ 71 #define FCS_AES_MIN_DATA_SIZE 0x20 /* 32 Byte */ 72 #define FCS_AES_CMD_MAX_WORD_SIZE 15U 73 74 #define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE 7U 75 #define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE 19U 76 #define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE 23U 77 #define FCS_MAC_VERIFY_RESP_MAX_WORD_SIZE 4U 78 #define FCS_SHA_HMAC_CRYPTO_PARAM_SIZE_OFFSET 8U 79 80 #define FCS_ECDSA_GET_PUBKEY_MAX_WORD_SIZE 5U 81 #define FCS_ECDSA_SHA2_DATA_SIGN_CMD_MAX_WORD_SIZE 7U 82 #define FCS_ECDSA_SHA2_DATA_SIG_VERIFY_CMD_MAX_WORD_SIZE 43U 83 /* FCS Payload Structure */ 84 typedef struct fcs_rng_payload_t { 85 uint32_t session_id; 86 uint32_t context_id; 87 uint32_t crypto_header; 88 uint32_t size; 89 } fcs_rng_payload; 90 91 typedef struct fcs_encrypt_payload_t { 92 uint32_t first_word; 93 uint32_t src_addr; 94 uint32_t src_size; 95 uint32_t dst_addr; 96 uint32_t dst_size; 97 } fcs_encrypt_payload; 98 99 typedef struct fcs_decrypt_payload_t { 100 uint32_t first_word; 101 uint32_t owner_id[2]; 102 uint32_t src_addr; 103 uint32_t src_size; 104 uint32_t dst_addr; 105 uint32_t dst_size; 106 } fcs_decrypt_payload; 107 108 typedef struct fcs_encrypt_ext_payload_t { 109 uint32_t session_id; 110 uint32_t context_id; 111 uint32_t crypto_header; 112 uint32_t src_addr; 113 uint32_t src_size; 114 uint32_t dst_addr; 115 uint32_t dst_size; 116 } fcs_encrypt_ext_payload; 117 118 typedef struct fcs_decrypt_ext_payload_t { 119 uint32_t session_id; 120 uint32_t context_id; 121 uint32_t crypto_header; 122 uint32_t owner_id[2]; 123 uint32_t src_addr; 124 uint32_t src_size; 125 uint32_t dst_addr; 126 uint32_t dst_size; 127 } fcs_decrypt_ext_payload; 128 129 typedef struct psgsigma_teardown_msg_t { 130 uint32_t reserved_word; 131 uint32_t magic_word; 132 uint32_t session_id; 133 } psgsigma_teardown_msg; 134 135 typedef struct fcs_cntr_set_preauth_payload_t { 136 uint32_t first_word; 137 uint32_t counter_value; 138 } fcs_cntr_set_preauth_payload; 139 140 typedef struct fcs_cs_key_payload_t { 141 uint32_t session_id; 142 uint32_t reserved0; 143 uint32_t reserved1; 144 uint32_t key_id; 145 } fcs_cs_key_payload; 146 147 typedef struct fcs_crypto_service_data_t { 148 uint32_t session_id; 149 uint32_t context_id; 150 uint32_t key_id; 151 uint32_t crypto_param_size; 152 uint64_t crypto_param; 153 } fcs_crypto_service_data; 154 155 typedef struct fcs_crypto_service_aes_data_t { 156 uint32_t session_id; 157 uint32_t context_id; 158 uint32_t param_size; 159 uint32_t key_id; 160 uint32_t crypto_param[7]; 161 } fcs_crypto_service_aes_data; 162 163 /* Functions Definitions */ 164 165 uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, 166 uint32_t *mbox_error); 167 int intel_fcs_random_number_gen_ext(uint32_t session_id, uint32_t context_id, 168 uint32_t size, uint32_t *send_id); 169 uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size, 170 uint32_t *send_id); 171 uint32_t intel_fcs_get_provision_data(uint32_t *send_id); 172 uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type, 173 int32_t counter_value, 174 uint32_t test_bit, 175 uint32_t *mbox_error); 176 uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size, 177 uint32_t dst_addr, uint32_t dst_size, 178 uint32_t *send_id); 179 180 uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size, 181 uint32_t dst_addr, uint32_t dst_size, 182 uint32_t *send_id); 183 184 int intel_fcs_encryption_ext(uint32_t session_id, uint32_t context_id, 185 uint32_t src_addr, uint32_t src_size, 186 uint32_t dst_addr, uint32_t *dst_size, 187 uint32_t *mbox_error); 188 int intel_fcs_decryption_ext(uint32_t sesion_id, uint32_t context_id, 189 uint32_t src_addr, uint32_t src_size, 190 uint32_t dst_addr, uint32_t *dst_size, 191 uint32_t *mbox_error); 192 193 int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error); 194 int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error); 195 int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size, 196 uint64_t dst_addr, uint32_t *dst_size, 197 uint32_t *mbox_error); 198 int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size, 199 uint64_t dst_addr, uint32_t *dst_size, 200 uint32_t *mbox_error); 201 uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, 202 uint32_t *mbox_error); 203 204 int intel_fcs_create_cert_on_reload(uint32_t cert_request, 205 uint32_t *mbox_error); 206 int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr, 207 uint32_t *dst_size, uint32_t *mbox_error); 208 209 int intel_fcs_open_crypto_service_session(uint32_t *session_id, 210 uint32_t *mbox_error); 211 int intel_fcs_close_crypto_service_session(uint32_t session_id, 212 uint32_t *mbox_error); 213 214 int intel_fcs_import_crypto_service_key(uint64_t src_addr, uint32_t src_size, 215 uint32_t *mbox_error); 216 int intel_fcs_export_crypto_service_key(uint32_t session_id, uint32_t key_id, 217 uint64_t dst_addr, uint32_t *dst_size, 218 uint32_t *mbox_error); 219 int intel_fcs_remove_crypto_service_key(uint32_t session_id, uint32_t key_id, 220 uint32_t *mbox_error); 221 int intel_fcs_get_crypto_service_key_info(uint32_t session_id, uint32_t key_id, 222 uint64_t dst_addr, uint32_t *dst_size, 223 uint32_t *mbox_error); 224 225 int intel_fcs_get_digest_init(uint32_t session_id, uint32_t context_id, 226 uint32_t key_id, uint32_t param_size, 227 uint64_t param_data, uint32_t *mbox_error); 228 int intel_fcs_get_digest_finalize(uint32_t session_id, uint32_t context_id, 229 uint32_t src_addr, uint32_t src_size, 230 uint64_t dst_addr, uint32_t *dst_size, 231 uint32_t *mbox_error); 232 233 int intel_fcs_mac_verify_init(uint32_t session_id, uint32_t context_id, 234 uint32_t key_id, uint32_t param_size, 235 uint64_t param_data, uint32_t *mbox_error); 236 int intel_fcs_mac_verify_finalize(uint32_t session_id, uint32_t context_id, 237 uint32_t src_addr, uint32_t src_size, 238 uint64_t dst_addr, uint32_t *dst_size, 239 uint32_t data_size, uint32_t *mbox_error); 240 241 int intel_fcs_ecdsa_sha2_data_sign_init(uint32_t session_id, 242 uint32_t context_id, uint32_t key_id, 243 uint32_t param_size, uint64_t param_data, 244 uint32_t *mbox_error); 245 int intel_fcs_ecdsa_sha2_data_sign_finalize(uint32_t session_id, 246 uint32_t context_id, uint32_t src_addr, 247 uint32_t src_size, uint64_t dst_addr, 248 uint32_t *dst_size, uint32_t *mbox_error); 249 250 int intel_fcs_ecdsa_sha2_data_sig_verify_init(uint32_t session_id, 251 uint32_t context_id, uint32_t key_id, 252 uint32_t param_size, uint64_t param_data, 253 uint32_t *mbox_error); 254 int intel_fcs_ecdsa_sha2_data_sig_verify_finalize(uint32_t session_id, 255 uint32_t context_id, uint32_t src_addr, 256 uint32_t src_size, uint64_t dst_addr, 257 uint32_t *dst_size, uint32_t data_size, 258 uint32_t *mbox_error); 259 260 int intel_fcs_ecdsa_get_pubkey_init(uint32_t session_id, uint32_t context_id, 261 uint32_t key_id, uint32_t param_size, 262 uint64_t param_data, uint32_t *mbox_error); 263 int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t session_id, uint32_t context_id, 264 uint64_t dst_addr, uint32_t *dst_size, 265 uint32_t *mbox_error); 266 267 int intel_fcs_aes_crypt_init(uint32_t session_id, uint32_t context_id, 268 uint32_t key_id, uint64_t param_addr, 269 uint32_t param_size, uint32_t *mbox_error); 270 int intel_fcs_aes_crypt_finalize(uint32_t session_id, uint32_t context_id, 271 uint64_t src_addr, uint32_t src_size, 272 uint64_t dst_addr, uint32_t dst_size, 273 uint32_t *send_id); 274 275 #endif /* SOCFPGA_FCS_H */ 276