xref: /rk3399_ARM-atf/plat/intel/soc/common/include/socfpga_fcs.h (revision 07912da1b7663451493fb5e40e4c33deeb18a639)
1 /*
2  * Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef SOCFPGA_FCS_H
8 #define SOCFPGA_FCS_H
9 
10 /* FCS Definitions */
11 
12 #define FCS_RANDOM_WORD_SIZE			8U
13 #define FCS_PROV_DATA_WORD_SIZE			44U
14 #define FCS_SHA384_WORD_SIZE			12U
15 
16 #define FCS_RANDOM_BYTE_SIZE			(FCS_RANDOM_WORD_SIZE * 4U)
17 #define FCS_RANDOM_EXT_MAX_WORD_SIZE		1020U
18 #define FCS_PROV_DATA_BYTE_SIZE			(FCS_PROV_DATA_WORD_SIZE * 4U)
19 #define FCS_SHA384_BYTE_SIZE			(FCS_SHA384_WORD_SIZE * 4U)
20 
21 #define FCS_RANDOM_EXT_OFFSET			3
22 
23 #define FCS_MODE_DECRYPT			0x0
24 #define FCS_MODE_ENCRYPT			0x1
25 #define FCS_ENCRYPTION_DATA_0			0x10100
26 #define FCS_DECRYPTION_DATA_0			0x10102
27 #define FCS_OWNER_ID_OFFSET			0xC
28 #define FCS_CRYPTION_CRYPTO_HEADER		0x07000000
29 #define FCS_CRYPTION_RESP_WORD_SIZE		4U
30 #define FCS_CRYPTION_RESP_SIZE_OFFSET		3U
31 
32 #define PSGSIGMA_TEARDOWN_MAGIC			0xB852E2A4
33 #define	PSGSIGMA_SESSION_ID_ONE			0x1
34 #define PSGSIGMA_UNKNOWN_SESSION		0xFFFFFFFF
35 
36 #define	RESERVED_AS_ZERO			0x0
37 /* FCS Single cert */
38 
39 #define FCS_BIG_CNTR_SEL			0x1
40 
41 #define FCS_SVN_CNTR_0_SEL			0x2
42 #define FCS_SVN_CNTR_1_SEL			0x3
43 #define FCS_SVN_CNTR_2_SEL			0x4
44 #define FCS_SVN_CNTR_3_SEL			0x5
45 
46 #define FCS_BIG_CNTR_VAL_MAX			495U
47 #define FCS_SVN_CNTR_VAL_MAX			64U
48 
49 /* FCS Attestation Cert Request Parameter */
50 
51 #define FCS_ALIAS_CERT				0x01
52 #define FCS_DEV_ID_SELF_SIGN_CERT		0x02
53 #define FCS_DEV_ID_ENROLL_CERT			0x04
54 #define FCS_ENROLL_SELF_SIGN_CERT		0x08
55 #define FCS_PLAT_KEY_CERT			0x10
56 
57 /* FCS Crypto Service */
58 
59 #define FCS_CS_KEY_OBJ_MAX_WORD_SIZE		88U
60 #define FCS_CS_KEY_INFO_MAX_WORD_SIZE		36U
61 #define FCS_CS_KEY_RESP_STATUS_MASK		0xFF
62 #define FCS_CS_KEY_RESP_STATUS_OFFSET		16U
63 
64 #define FCS_CS_FIELD_SIZE_MASK			0xFFFF
65 #define FCS_CS_FIELD_FLAG_OFFSET		24
66 #define FCS_CS_FIELD_FLAG_INIT			BIT(0)
67 #define FCS_CS_FIELD_FLAG_UPDATE		BIT(1)
68 #define FCS_CS_FIELD_FLAG_FINALIZE		BIT(2)
69 
70 #define FCS_AES_MAX_DATA_SIZE			0x10000000	/* 256 MB */
71 #define FCS_AES_MIN_DATA_SIZE			0x20		/* 32 Byte */
72 #define FCS_AES_CMD_MAX_WORD_SIZE		15U
73 
74 #define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE	7U
75 #define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE	19U
76 #define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE	23U
77 #define FCS_MAC_VERIFY_RESP_MAX_WORD_SIZE	4U
78 #define FCS_SHA_HMAC_CRYPTO_PARAM_SIZE_OFFSET	8U
79 
80 #define FCS_ECDSA_GET_PUBKEY_MAX_WORD_SIZE	5U
81 #define FCS_ECDSA_SHA2_DATA_SIGN_CMD_MAX_WORD_SIZE	7U
82 /* FCS Payload Structure */
83 typedef struct fcs_rng_payload_t {
84 	uint32_t session_id;
85 	uint32_t context_id;
86 	uint32_t crypto_header;
87 	uint32_t size;
88 } fcs_rng_payload;
89 
90 typedef struct fcs_encrypt_payload_t {
91 	uint32_t first_word;
92 	uint32_t src_addr;
93 	uint32_t src_size;
94 	uint32_t dst_addr;
95 	uint32_t dst_size;
96 } fcs_encrypt_payload;
97 
98 typedef struct fcs_decrypt_payload_t {
99 	uint32_t first_word;
100 	uint32_t owner_id[2];
101 	uint32_t src_addr;
102 	uint32_t src_size;
103 	uint32_t dst_addr;
104 	uint32_t dst_size;
105 } fcs_decrypt_payload;
106 
107 typedef struct fcs_encrypt_ext_payload_t {
108 	uint32_t session_id;
109 	uint32_t context_id;
110 	uint32_t crypto_header;
111 	uint32_t src_addr;
112 	uint32_t src_size;
113 	uint32_t dst_addr;
114 	uint32_t dst_size;
115 } fcs_encrypt_ext_payload;
116 
117 typedef struct fcs_decrypt_ext_payload_t {
118 	uint32_t session_id;
119 	uint32_t context_id;
120 	uint32_t crypto_header;
121 	uint32_t owner_id[2];
122 	uint32_t src_addr;
123 	uint32_t src_size;
124 	uint32_t dst_addr;
125 	uint32_t dst_size;
126 } fcs_decrypt_ext_payload;
127 
128 typedef struct psgsigma_teardown_msg_t {
129 	uint32_t reserved_word;
130 	uint32_t magic_word;
131 	uint32_t session_id;
132 } psgsigma_teardown_msg;
133 
134 typedef struct fcs_cntr_set_preauth_payload_t {
135 	uint32_t first_word;
136 	uint32_t counter_value;
137 } fcs_cntr_set_preauth_payload;
138 
139 typedef struct fcs_cs_key_payload_t {
140 	uint32_t session_id;
141 	uint32_t reserved0;
142 	uint32_t reserved1;
143 	uint32_t key_id;
144 } fcs_cs_key_payload;
145 
146 typedef struct fcs_crypto_service_data_t {
147 	uint32_t session_id;
148 	uint32_t context_id;
149 	uint32_t key_id;
150 	uint32_t crypto_param_size;
151 	uint64_t crypto_param;
152 } fcs_crypto_service_data;
153 
154 typedef struct fcs_crypto_service_aes_data_t {
155 	uint32_t session_id;
156 	uint32_t context_id;
157 	uint32_t param_size;
158 	uint32_t key_id;
159 	uint32_t crypto_param[7];
160 } fcs_crypto_service_aes_data;
161 
162 /* Functions Definitions */
163 
164 uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size,
165 				uint32_t *mbox_error);
166 int intel_fcs_random_number_gen_ext(uint32_t session_id, uint32_t context_id,
167 				uint32_t size, uint32_t *send_id);
168 uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size,
169 				uint32_t *send_id);
170 uint32_t intel_fcs_get_provision_data(uint32_t *send_id);
171 uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type,
172 				int32_t counter_value,
173 				uint32_t test_bit,
174 				uint32_t *mbox_error);
175 uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size,
176 				uint32_t dst_addr, uint32_t dst_size,
177 				uint32_t *send_id);
178 
179 uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size,
180 				uint32_t dst_addr, uint32_t dst_size,
181 				uint32_t *send_id);
182 
183 int intel_fcs_encryption_ext(uint32_t session_id, uint32_t context_id,
184 				uint32_t src_addr, uint32_t src_size,
185 				uint32_t dst_addr, uint32_t *dst_size,
186 				uint32_t *mbox_error);
187 int intel_fcs_decryption_ext(uint32_t sesion_id, uint32_t context_id,
188 				uint32_t src_addr, uint32_t src_size,
189 				uint32_t dst_addr, uint32_t *dst_size,
190 				uint32_t *mbox_error);
191 
192 int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error);
193 int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error);
194 int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size,
195 				uint64_t dst_addr, uint32_t *dst_size,
196 				uint32_t *mbox_error);
197 int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size,
198 				uint64_t dst_addr, uint32_t *dst_size,
199 				uint32_t *mbox_error);
200 uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size,
201 				uint32_t *mbox_error);
202 
203 int intel_fcs_create_cert_on_reload(uint32_t cert_request,
204 				uint32_t *mbox_error);
205 int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr,
206 				uint32_t *dst_size, uint32_t *mbox_error);
207 
208 int intel_fcs_open_crypto_service_session(uint32_t *session_id,
209 				uint32_t *mbox_error);
210 int intel_fcs_close_crypto_service_session(uint32_t session_id,
211 				uint32_t *mbox_error);
212 
213 int intel_fcs_import_crypto_service_key(uint64_t src_addr, uint32_t src_size,
214 				uint32_t *mbox_error);
215 int intel_fcs_export_crypto_service_key(uint32_t session_id, uint32_t key_id,
216 				uint64_t dst_addr, uint32_t *dst_size,
217 				uint32_t *mbox_error);
218 int intel_fcs_remove_crypto_service_key(uint32_t session_id, uint32_t key_id,
219 				uint32_t *mbox_error);
220 int intel_fcs_get_crypto_service_key_info(uint32_t session_id, uint32_t key_id,
221 				uint64_t dst_addr, uint32_t *dst_size,
222 				uint32_t *mbox_error);
223 
224 int intel_fcs_get_digest_init(uint32_t session_id, uint32_t context_id,
225 				uint32_t key_id, uint32_t param_size,
226 				uint64_t param_data, uint32_t *mbox_error);
227 int intel_fcs_get_digest_finalize(uint32_t session_id, uint32_t context_id,
228 				uint32_t src_addr, uint32_t src_size,
229 				uint64_t dst_addr, uint32_t *dst_size,
230 				uint32_t *mbox_error);
231 
232 int intel_fcs_mac_verify_init(uint32_t session_id, uint32_t context_id,
233 				uint32_t key_id, uint32_t param_size,
234 				uint64_t param_data, uint32_t *mbox_error);
235 int intel_fcs_mac_verify_finalize(uint32_t session_id, uint32_t context_id,
236 				uint32_t src_addr, uint32_t src_size,
237 				uint64_t dst_addr, uint32_t *dst_size,
238 				uint32_t data_size, uint32_t *mbox_error);
239 
240 int intel_fcs_ecdsa_sha2_data_sign_init(uint32_t session_id,
241 				uint32_t context_id, uint32_t key_id,
242 				uint32_t param_size, uint64_t param_data,
243 				uint32_t *mbox_error);
244 int intel_fcs_ecdsa_sha2_data_sign_finalize(uint32_t session_id,
245 				uint32_t context_id, uint32_t src_addr,
246 				uint32_t src_size, uint64_t dst_addr,
247 				uint32_t *dst_size, uint32_t *mbox_error);
248 
249 int intel_fcs_ecdsa_get_pubkey_init(uint32_t session_id, uint32_t context_id,
250 				uint32_t key_id, uint32_t param_size,
251 				uint64_t param_data, uint32_t *mbox_error);
252 int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t session_id, uint32_t context_id,
253 				uint64_t dst_addr, uint32_t *dst_size,
254 				uint32_t *mbox_error);
255 
256 int intel_fcs_aes_crypt_init(uint32_t session_id, uint32_t context_id,
257 				uint32_t key_id, uint64_t param_addr,
258 				uint32_t param_size, uint32_t *mbox_error);
259 int intel_fcs_aes_crypt_finalize(uint32_t session_id, uint32_t context_id,
260 				uint64_t src_addr, uint32_t src_size,
261 				uint64_t dst_addr, uint32_t dst_size,
262 				uint32_t *send_id);
263 
264 #endif /* SOCFPGA_FCS_H */
265