1286b96f4SSieu Mun Tang /* 2286b96f4SSieu Mun Tang * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3286b96f4SSieu Mun Tang * 4286b96f4SSieu Mun Tang * SPDX-License-Identifier: BSD-3-Clause 5286b96f4SSieu Mun Tang */ 6286b96f4SSieu Mun Tang 7286b96f4SSieu Mun Tang #ifndef SOCFPGA_FCS_H 8286b96f4SSieu Mun Tang #define SOCFPGA_FCS_H 9286b96f4SSieu Mun Tang 10286b96f4SSieu Mun Tang /* FCS Definitions */ 11286b96f4SSieu Mun Tang 12286b96f4SSieu Mun Tang #define FCS_RANDOM_WORD_SIZE 8U 13286b96f4SSieu Mun Tang #define FCS_PROV_DATA_WORD_SIZE 44U 1477902fcaSSieu Mun Tang #define FCS_SHA384_WORD_SIZE 12U 15286b96f4SSieu Mun Tang 16286b96f4SSieu Mun Tang #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) 17286b96f4SSieu Mun Tang #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) 1877902fcaSSieu Mun Tang #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) 19286b96f4SSieu Mun Tang 2002d3ef33SSieu Mun Tang #define FCS_MODE_DECRYPT 0x0 2102d3ef33SSieu Mun Tang #define FCS_MODE_ENCRYPT 0x1 2202d3ef33SSieu Mun Tang #define FCS_ENCRYPTION_DATA_0 0x10100 2302d3ef33SSieu Mun Tang #define FCS_DECRYPTION_DATA_0 0x10102 2402d3ef33SSieu Mun Tang #define FCS_OWNER_ID_OFFSET 0xC 25286b96f4SSieu Mun Tang 26*d1740831SSieu Mun Tang #define PSGSIGMA_TEARDOWN_MAGIC 0xB852E2A4 27*d1740831SSieu Mun Tang #define PSGSIGMA_SESSION_ID_ONE 0x1 28*d1740831SSieu Mun Tang #define PSGSIGMA_UNKNOWN_SESSION 0xFFFFFFFF 29*d1740831SSieu Mun Tang 30*d1740831SSieu Mun Tang #define RESERVED_AS_ZERO 0x0 31*d1740831SSieu Mun Tang 32286b96f4SSieu Mun Tang /* FCS Payload Structure */ 33286b96f4SSieu Mun Tang 3402d3ef33SSieu Mun Tang typedef struct fcs_encrypt_payload_t { 35286b96f4SSieu Mun Tang uint32_t first_word; 36286b96f4SSieu Mun Tang uint32_t src_addr; 37286b96f4SSieu Mun Tang uint32_t src_size; 38286b96f4SSieu Mun Tang uint32_t dst_addr; 39286b96f4SSieu Mun Tang uint32_t dst_size; 4002d3ef33SSieu Mun Tang } fcs_encrypt_payload; 4102d3ef33SSieu Mun Tang 4202d3ef33SSieu Mun Tang typedef struct fcs_decrypt_payload_t { 4302d3ef33SSieu Mun Tang uint32_t first_word; 4402d3ef33SSieu Mun Tang uint32_t owner_id[2]; 4502d3ef33SSieu Mun Tang uint32_t src_addr; 4602d3ef33SSieu Mun Tang uint32_t src_size; 4702d3ef33SSieu Mun Tang uint32_t dst_addr; 4802d3ef33SSieu Mun Tang uint32_t dst_size; 4902d3ef33SSieu Mun Tang } fcs_decrypt_payload; 50286b96f4SSieu Mun Tang 51*d1740831SSieu Mun Tang typedef struct psgsigma_teardown_msg_t { 52*d1740831SSieu Mun Tang uint32_t reserved_word; 53*d1740831SSieu Mun Tang uint32_t magic_word; 54*d1740831SSieu Mun Tang uint32_t session_id; 55*d1740831SSieu Mun Tang } psgsigma_teardown_msg; 56*d1740831SSieu Mun Tang 57*d1740831SSieu Mun Tang 58286b96f4SSieu Mun Tang /* Functions Definitions */ 59286b96f4SSieu Mun Tang 60286b96f4SSieu Mun Tang uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, 61286b96f4SSieu Mun Tang uint32_t *mbox_error); 62286b96f4SSieu Mun Tang uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size, 63286b96f4SSieu Mun Tang uint32_t *send_id); 64286b96f4SSieu Mun Tang uint32_t intel_fcs_get_provision_data(uint32_t *send_id); 6502d3ef33SSieu Mun Tang uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size, 6602d3ef33SSieu Mun Tang uint32_t dst_addr, uint32_t dst_size, 6702d3ef33SSieu Mun Tang uint32_t *send_id); 6802d3ef33SSieu Mun Tang 6902d3ef33SSieu Mun Tang uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size, 7002d3ef33SSieu Mun Tang uint32_t dst_addr, uint32_t dst_size, 7102d3ef33SSieu Mun Tang uint32_t *send_id); 72286b96f4SSieu Mun Tang 73*d1740831SSieu Mun Tang int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error); 74*d1740831SSieu Mun Tang int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error); 75*d1740831SSieu Mun Tang int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size, 76*d1740831SSieu Mun Tang uint64_t dst_addr, uint32_t *dst_size, 77*d1740831SSieu Mun Tang uint32_t *mbox_error); 78*d1740831SSieu Mun Tang int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size, 79*d1740831SSieu Mun Tang uint64_t dst_addr, uint32_t *dst_size, 80*d1740831SSieu Mun Tang uint32_t *mbox_error); 8177902fcaSSieu Mun Tang uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, 8277902fcaSSieu Mun Tang uint32_t *mbox_error); 8377902fcaSSieu Mun Tang 84286b96f4SSieu Mun Tang #endif /* SOCFPGA_FCS_H */ 85