1286b96f4SSieu Mun Tang /* 2286b96f4SSieu Mun Tang * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3286b96f4SSieu Mun Tang * 4286b96f4SSieu Mun Tang * SPDX-License-Identifier: BSD-3-Clause 5286b96f4SSieu Mun Tang */ 6286b96f4SSieu Mun Tang 7286b96f4SSieu Mun Tang #ifndef SOCFPGA_FCS_H 8286b96f4SSieu Mun Tang #define SOCFPGA_FCS_H 9286b96f4SSieu Mun Tang 10286b96f4SSieu Mun Tang /* FCS Definitions */ 11286b96f4SSieu Mun Tang 12286b96f4SSieu Mun Tang #define FCS_RANDOM_WORD_SIZE 8U 13286b96f4SSieu Mun Tang #define FCS_PROV_DATA_WORD_SIZE 44U 14*77902fcaSSieu Mun Tang #define FCS_SHA384_WORD_SIZE 12U 15286b96f4SSieu Mun Tang 16286b96f4SSieu Mun Tang #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) 17286b96f4SSieu Mun Tang #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) 18*77902fcaSSieu Mun Tang #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) 19286b96f4SSieu Mun Tang 20286b96f4SSieu Mun Tang #define FCS_CRYPTION_DATA_0 0x10100 21286b96f4SSieu Mun Tang 22286b96f4SSieu Mun Tang /* FCS Payload Structure */ 23286b96f4SSieu Mun Tang 24286b96f4SSieu Mun Tang typedef struct fcs_crypt_payload_t { 25286b96f4SSieu Mun Tang uint32_t first_word; 26286b96f4SSieu Mun Tang uint32_t src_addr; 27286b96f4SSieu Mun Tang uint32_t src_size; 28286b96f4SSieu Mun Tang uint32_t dst_addr; 29286b96f4SSieu Mun Tang uint32_t dst_size; 30286b96f4SSieu Mun Tang } fcs_crypt_payload; 31286b96f4SSieu Mun Tang 32286b96f4SSieu Mun Tang /* Functions Definitions */ 33286b96f4SSieu Mun Tang 34286b96f4SSieu Mun Tang uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, 35286b96f4SSieu Mun Tang uint32_t *mbox_error); 36286b96f4SSieu Mun Tang uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size, 37286b96f4SSieu Mun Tang uint32_t *send_id); 38286b96f4SSieu Mun Tang uint32_t intel_fcs_get_provision_data(uint32_t *send_id); 39286b96f4SSieu Mun Tang uint32_t intel_fcs_cryption(uint32_t mode, uint32_t src_addr, 40286b96f4SSieu Mun Tang uint32_t src_size, uint32_t dst_addr, 41286b96f4SSieu Mun Tang uint32_t dst_size, uint32_t *send_id); 42286b96f4SSieu Mun Tang 43*77902fcaSSieu Mun Tang uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, 44*77902fcaSSieu Mun Tang uint32_t *mbox_error); 45*77902fcaSSieu Mun Tang 46286b96f4SSieu Mun Tang #endif /* SOCFPGA_FCS_H */ 47