1286b96f4SSieu Mun Tang /* 2286b96f4SSieu Mun Tang * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3286b96f4SSieu Mun Tang * 4286b96f4SSieu Mun Tang * SPDX-License-Identifier: BSD-3-Clause 5286b96f4SSieu Mun Tang */ 6286b96f4SSieu Mun Tang 7286b96f4SSieu Mun Tang #ifndef SOCFPGA_FCS_H 8286b96f4SSieu Mun Tang #define SOCFPGA_FCS_H 9286b96f4SSieu Mun Tang 10286b96f4SSieu Mun Tang /* FCS Definitions */ 11286b96f4SSieu Mun Tang 12286b96f4SSieu Mun Tang #define FCS_RANDOM_WORD_SIZE 8U 13286b96f4SSieu Mun Tang #define FCS_PROV_DATA_WORD_SIZE 44U 1477902fcaSSieu Mun Tang #define FCS_SHA384_WORD_SIZE 12U 15286b96f4SSieu Mun Tang 16286b96f4SSieu Mun Tang #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) 17286b96f4SSieu Mun Tang #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) 1877902fcaSSieu Mun Tang #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) 19286b96f4SSieu Mun Tang 20*02d3ef33SSieu Mun Tang #define FCS_MODE_DECRYPT 0x0 21*02d3ef33SSieu Mun Tang #define FCS_MODE_ENCRYPT 0x1 22*02d3ef33SSieu Mun Tang #define FCS_ENCRYPTION_DATA_0 0x10100 23*02d3ef33SSieu Mun Tang #define FCS_DECRYPTION_DATA_0 0x10102 24*02d3ef33SSieu Mun Tang #define FCS_OWNER_ID_OFFSET 0xC 25286b96f4SSieu Mun Tang 26286b96f4SSieu Mun Tang /* FCS Payload Structure */ 27286b96f4SSieu Mun Tang 28*02d3ef33SSieu Mun Tang typedef struct fcs_encrypt_payload_t { 29286b96f4SSieu Mun Tang uint32_t first_word; 30286b96f4SSieu Mun Tang uint32_t src_addr; 31286b96f4SSieu Mun Tang uint32_t src_size; 32286b96f4SSieu Mun Tang uint32_t dst_addr; 33286b96f4SSieu Mun Tang uint32_t dst_size; 34*02d3ef33SSieu Mun Tang } fcs_encrypt_payload; 35*02d3ef33SSieu Mun Tang 36*02d3ef33SSieu Mun Tang typedef struct fcs_decrypt_payload_t { 37*02d3ef33SSieu Mun Tang uint32_t first_word; 38*02d3ef33SSieu Mun Tang uint32_t owner_id[2]; 39*02d3ef33SSieu Mun Tang uint32_t src_addr; 40*02d3ef33SSieu Mun Tang uint32_t src_size; 41*02d3ef33SSieu Mun Tang uint32_t dst_addr; 42*02d3ef33SSieu Mun Tang uint32_t dst_size; 43*02d3ef33SSieu Mun Tang } fcs_decrypt_payload; 44286b96f4SSieu Mun Tang 45286b96f4SSieu Mun Tang /* Functions Definitions */ 46286b96f4SSieu Mun Tang 47286b96f4SSieu Mun Tang uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, 48286b96f4SSieu Mun Tang uint32_t *mbox_error); 49286b96f4SSieu Mun Tang uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size, 50286b96f4SSieu Mun Tang uint32_t *send_id); 51286b96f4SSieu Mun Tang uint32_t intel_fcs_get_provision_data(uint32_t *send_id); 52*02d3ef33SSieu Mun Tang uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size, 53*02d3ef33SSieu Mun Tang uint32_t dst_addr, uint32_t dst_size, 54*02d3ef33SSieu Mun Tang uint32_t *send_id); 55*02d3ef33SSieu Mun Tang 56*02d3ef33SSieu Mun Tang uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size, 57*02d3ef33SSieu Mun Tang uint32_t dst_addr, uint32_t dst_size, 58*02d3ef33SSieu Mun Tang uint32_t *send_id); 59286b96f4SSieu Mun Tang 6077902fcaSSieu Mun Tang uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, 6177902fcaSSieu Mun Tang uint32_t *mbox_error); 6277902fcaSSieu Mun Tang 63286b96f4SSieu Mun Tang #endif /* SOCFPGA_FCS_H */ 64