xref: /rk3399_ARM-atf/plat/intel/soc/common/drivers/wdt/watchdog.c (revision bf719f66a7f2261b69b397072cec5ad99c573891)
1*bf719f66SHadi Asyrafi /*
2*bf719f66SHadi Asyrafi  * Copyright (c) 2019, Intel Corporation. All rights reserved.
3*bf719f66SHadi Asyrafi  *
4*bf719f66SHadi Asyrafi  * SPDX-License-Identifier: BSD-3-Clause
5*bf719f66SHadi Asyrafi  */
6*bf719f66SHadi Asyrafi 
7*bf719f66SHadi Asyrafi #include <common/debug.h>
8*bf719f66SHadi Asyrafi #include <lib/mmio.h>
9*bf719f66SHadi Asyrafi #include <platform_def.h>
10*bf719f66SHadi Asyrafi 
11*bf719f66SHadi Asyrafi #include "watchdog.h"
12*bf719f66SHadi Asyrafi 
13*bf719f66SHadi Asyrafi 
14*bf719f66SHadi Asyrafi /* Reset watchdog timer */
15*bf719f66SHadi Asyrafi void watchdog_sw_rst(void)
16*bf719f66SHadi Asyrafi {
17*bf719f66SHadi Asyrafi 	mmio_write_32(WDT_CRR, WDT_SW_RST);
18*bf719f66SHadi Asyrafi }
19*bf719f66SHadi Asyrafi 
20*bf719f66SHadi Asyrafi /* Print component information */
21*bf719f66SHadi Asyrafi void watchdog_info(void)
22*bf719f66SHadi Asyrafi {
23*bf719f66SHadi Asyrafi 	INFO("Component Type    : %x\r\n", mmio_read_32(WDT_COMP_VERSION));
24*bf719f66SHadi Asyrafi 	INFO("Component Version : %x\r\n", mmio_read_32(WDT_COMP_TYPE));
25*bf719f66SHadi Asyrafi }
26*bf719f66SHadi Asyrafi 
27*bf719f66SHadi Asyrafi /* Check watchdog current status */
28*bf719f66SHadi Asyrafi void watchdog_status(void)
29*bf719f66SHadi Asyrafi {
30*bf719f66SHadi Asyrafi 	if (mmio_read_32(WDT_CR) & 1) {
31*bf719f66SHadi Asyrafi 		INFO("Watchdog Timer in currently enabled\n");
32*bf719f66SHadi Asyrafi 		INFO("Current Counter : 0x%x\r\n", mmio_read_32(WDT_CCVR));
33*bf719f66SHadi Asyrafi 	} else {
34*bf719f66SHadi Asyrafi 		INFO("Watchdog Timer in currently disabled\n");
35*bf719f66SHadi Asyrafi 	}
36*bf719f66SHadi Asyrafi }
37*bf719f66SHadi Asyrafi 
38*bf719f66SHadi Asyrafi /* Initialize & enable watchdog */
39*bf719f66SHadi Asyrafi void watchdog_init(int watchdog_clk)
40*bf719f66SHadi Asyrafi {
41*bf719f66SHadi Asyrafi 	uint8_t cycles_i = 0;
42*bf719f66SHadi Asyrafi 	uint32_t wdt_cycles = WDT_MIN_CYCLES;
43*bf719f66SHadi Asyrafi 	uint32_t top_init_cycles = WDT_PERIOD * watchdog_clk;
44*bf719f66SHadi Asyrafi 
45*bf719f66SHadi Asyrafi 	while ((cycles_i < 15) && (wdt_cycles < top_init_cycles)) {
46*bf719f66SHadi Asyrafi 		wdt_cycles = (wdt_cycles << 1);
47*bf719f66SHadi Asyrafi 		cycles_i++;
48*bf719f66SHadi Asyrafi 	}
49*bf719f66SHadi Asyrafi 
50*bf719f66SHadi Asyrafi 	mmio_write_32(WDT_TORR, (cycles_i << 4) | cycles_i);
51*bf719f66SHadi Asyrafi 
52*bf719f66SHadi Asyrafi 	watchdog_enable();
53*bf719f66SHadi Asyrafi }
54*bf719f66SHadi Asyrafi 
55*bf719f66SHadi Asyrafi void watchdog_enable(void)
56*bf719f66SHadi Asyrafi {
57*bf719f66SHadi Asyrafi 	mmio_write_32(WDT_CR, WDT_CR_RMOD|WDT_CR_EN);
58*bf719f66SHadi Asyrafi }
59