xref: /rk3399_ARM-atf/plat/intel/soc/common/drivers/wdt/watchdog.c (revision b3257a3d39971663caf4da00b590958264ec46f8)
1bf719f66SHadi Asyrafi /*
2bf719f66SHadi Asyrafi  * Copyright (c) 2019, Intel Corporation. All rights reserved.
3bf719f66SHadi Asyrafi  *
4bf719f66SHadi Asyrafi  * SPDX-License-Identifier: BSD-3-Clause
5bf719f66SHadi Asyrafi  */
6bf719f66SHadi Asyrafi 
7bf719f66SHadi Asyrafi #include <common/debug.h>
8bf719f66SHadi Asyrafi #include <lib/mmio.h>
9bf719f66SHadi Asyrafi 
10bf719f66SHadi Asyrafi #include "watchdog.h"
11bf719f66SHadi Asyrafi 
12bf719f66SHadi Asyrafi 
13bf719f66SHadi Asyrafi /* Reset watchdog timer */
watchdog_sw_rst(void)14bf719f66SHadi Asyrafi void watchdog_sw_rst(void)
15bf719f66SHadi Asyrafi {
16bf719f66SHadi Asyrafi 	mmio_write_32(WDT_CRR, WDT_SW_RST);
17bf719f66SHadi Asyrafi }
18bf719f66SHadi Asyrafi 
19bf719f66SHadi Asyrafi /* Print component information */
watchdog_info(void)20bf719f66SHadi Asyrafi void watchdog_info(void)
21bf719f66SHadi Asyrafi {
22bf719f66SHadi Asyrafi 	INFO("Component Type    : %x\r\n", mmio_read_32(WDT_COMP_VERSION));
23bf719f66SHadi Asyrafi 	INFO("Component Version : %x\r\n", mmio_read_32(WDT_COMP_TYPE));
24bf719f66SHadi Asyrafi }
25bf719f66SHadi Asyrafi 
26bf719f66SHadi Asyrafi /* Check watchdog current status */
watchdog_status(void)27bf719f66SHadi Asyrafi void watchdog_status(void)
28bf719f66SHadi Asyrafi {
29bf719f66SHadi Asyrafi 	if (mmio_read_32(WDT_CR) & 1) {
30*19e36445SHadi Asyrafi 		INFO("Watchdog Timer is currently enabled\n");
31bf719f66SHadi Asyrafi 		INFO("Current Counter : 0x%x\r\n", mmio_read_32(WDT_CCVR));
32bf719f66SHadi Asyrafi 	} else {
33*19e36445SHadi Asyrafi 		INFO("Watchdog Timer is currently disabled\n");
34bf719f66SHadi Asyrafi 	}
35bf719f66SHadi Asyrafi }
36bf719f66SHadi Asyrafi 
37bf719f66SHadi Asyrafi /* Initialize & enable watchdog */
watchdog_init(int watchdog_clk)38bf719f66SHadi Asyrafi void watchdog_init(int watchdog_clk)
39bf719f66SHadi Asyrafi {
40bf719f66SHadi Asyrafi 	uint8_t cycles_i = 0;
41bf719f66SHadi Asyrafi 	uint32_t wdt_cycles = WDT_MIN_CYCLES;
42bf719f66SHadi Asyrafi 	uint32_t top_init_cycles = WDT_PERIOD * watchdog_clk;
43bf719f66SHadi Asyrafi 
44bf719f66SHadi Asyrafi 	while ((cycles_i < 15) && (wdt_cycles < top_init_cycles)) {
45bf719f66SHadi Asyrafi 		wdt_cycles = (wdt_cycles << 1);
46bf719f66SHadi Asyrafi 		cycles_i++;
47bf719f66SHadi Asyrafi 	}
48bf719f66SHadi Asyrafi 
49bf719f66SHadi Asyrafi 	mmio_write_32(WDT_TORR, (cycles_i << 4) | cycles_i);
50bf719f66SHadi Asyrafi 
51bf719f66SHadi Asyrafi 	mmio_write_32(WDT_CR, WDT_CR_RMOD|WDT_CR_EN);
52bf719f66SHadi Asyrafi }
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