1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CAD_QSPI_H 8 #define CAD_QSPI_H 9 10 #define CAD_QSPI_MICRON_N25Q_SUPPORT 1 11 12 #define CAD_QSPI_OFFSET 0xff8d2000 13 14 #define CAD_INVALID -1 15 #define CAD_QSPI_ERROR -2 16 17 #define CAD_QSPI_ADDR_FASTREAD 0 18 #define CAD_QSPI_ADDR_FASTREAD_DUAL_IO 1 19 #define CAD_QSPI_ADDR_FASTREAD_QUAD_IO 2 20 #define CAT_QSPI_ADDR_SINGLE_IO 0 21 #define CAT_QSPI_ADDR_DUAL_IO 1 22 #define CAT_QSPI_ADDR_QUAD_IO 2 23 24 #define CAD_QSPI_BANK_ADDR(x) ((x) >> 24) 25 #define CAD_QSPI_BANK_ADDR_MSK 0xff000000 26 27 #define CAD_QSPI_COMMAND_TIMEOUT 0x10000000 28 29 #define CAD_QSPI_CFG 0x0 30 #define CAD_QSPI_CFG_BAUDDIV_MSK 0xff87ffff 31 #define CAD_QSPI_CFG_BAUDDIV(x) (((x) << 19) & 0x780000) 32 #define CAD_QSPI_CFG_CS_MSK ~0x3c00 33 #define CAD_QSPI_CFG_CS(x) (((x) << 11)) 34 #define CAD_QSPI_CFG_ENABLE (1 << 0) 35 #define CAD_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff 36 #define CAD_QSPI_CFG_IDLE (1 << 31) 37 #define CAD_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb 38 #define CAD_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd 39 40 #define CAD_QSPIDATA_OFST 0xff900000 41 42 #define CAD_QSPI_DELAY 0xc 43 #define CAD_QSPI_DELAY_CSSOT(x) (((x) & 0xff) << 0) 44 #define CAD_QSPI_DELAY_CSEOT(x) (((x) & 0xff) << 8) 45 #define CAD_QSPI_DELAY_CSDADS(x) (((x) & 0xff) << 16) 46 #define CAD_QSPI_DELAY_CSDA(x) (((x) & 0xff) << 24) 47 48 #define CAD_QSPI_DEVSZ 0x14 49 #define CAD_QSPI_DEVSZ_ADDR_BYTES(x) ((x) << 0) 50 #define CAD_QSPI_DEVSZ_BYTES_PER_PAGE(x) ((x) << 4) 51 #define CAD_QSPI_DEVSZ_BYTES_PER_BLOCK(x) ((x) << 16) 52 53 #define CAD_QSPI_DEVWR 0x8 54 #define CAD_QSPI_DEVRD 0x4 55 #define CAD_QSPI_DEV_OPCODE(x) (((x) & 0xff) << 0) 56 #define CAD_QSPI_DEV_INST_TYPE(x) (((x) & 0x03) << 8) 57 #define CAD_QSPI_DEV_ADDR_TYPE(x) (((x) & 0x03) << 12) 58 #define CAD_QSPI_DEV_DATA_TYPE(x) (((x) & 0x03) << 16) 59 #define CAD_QSPI_DEV_MODE_BIT(x) (((x) & 0x01) << 20) 60 #define CAD_QSPI_DEV_DUMMY_CLK_CYCLE(x) (((x) & 0x0f) << 24) 61 62 #define CAD_QSPI_FLASHCMD 0x90 63 #define CAD_QSPI_FLASHCMD_ADDR 0x94 64 #define CAD_QSPI_FLASHCMD_EXECUTE 0x1 65 #define CAD_QSPI_FLASHCMD_EXECUTE_STAT 0x2 66 #define CAD_QSPI_FLASHCMD_NUM_DUMMYBYTES_MAX 5 67 #define CAD_QSPI_FLASHCMD_NUM_DUMMYBYTES(x) (((x) << 7) & 0x000f80) 68 #define CAD_QSPI_FLASHCMD_OPCODE(x) (((x) & 0xff) << 24) 69 #define CAD_QSPI_FLASHCMD_ENRDDATA(x) (((x) & 1) << 23) 70 #define CAD_QSPI_FLASHCMD_NUMRDDATABYTES(x) (((x) & 0xf) << 20) 71 #define CAD_QSPI_FLASHCMD_ENCMDADDR(x) (((x) & 1) << 19) 72 #define CAD_QSPI_FLASHCMD_ENMODEBIT(x) (((x) & 1) << 18) 73 #define CAD_QSPI_FLASHCMD_NUMADDRBYTES(x) (((x) & 0x3) << 16) 74 #define CAD_QSPI_FLASHCMD_ENWRDATA(x) (((x) & 1) << 15) 75 #define CAD_QSPI_FLASHCMD_NUMWRDATABYTES(x) (((x) & 0x7) << 12) 76 #define CAD_QSPI_FLASHCMD_NUMDUMMYBYTES(x) (((x) & 0x1f) << 7) 77 #define CAD_QSPI_FLASHCMD_RDDATA0 0xa0 78 #define CAD_QSPI_FLASHCMD_RDDATA1 0xa4 79 #define CAD_QSPI_FLASHCMD_WRDATA0 0xa8 80 #define CAD_QSPI_FLASHCMD_WRDATA1 0xac 81 82 #define CAD_QSPI_RDDATACAP 0x10 83 #define CAD_QSPI_RDDATACAP_BYP(x) (((x) & 1) << 0) 84 #define CAD_QSPI_RDDATACAP_DELAY(x) (((x) & 0xf) << 1) 85 86 #define CAD_QSPI_REMAPADDR 0x24 87 #define CAD_QSPI_REMAPADDR_VALUE_SET(x) (((x) & 0xffffffff) << 0) 88 89 #define CAD_QSPI_SRAMPART 0x18 90 #define CAD_QSPI_SRAMFILL 0x2c 91 #define CAD_QSPI_SRAMPART_ADDR(x) (((x) >> 0) & 0x3ff) 92 #define CAD_QSPI_SRAM_FIFO_ENTRY_COUNT (512 / sizeof(uint32_t)) 93 #define CAD_QSPI_SRAMFILL_INDWRPART(x) (((x) >> 16) & 0x00ffff) 94 #define CAD_QSPI_SRAMFILL_INDRDPART(x) (((x) >> 0) & 0x00ffff) 95 96 #define CAD_QSPI_SELCLKPHASE(x) (((x) & 1) << 2) 97 #define CAD_QSPI_SELCLKPOL(x) (((x) & 1) << 1) 98 99 #define CAD_QSPI_STIG_FLAGSR_PROGRAMREADY(x) (((x) >> 7) & 1) 100 #define CAD_QSPI_STIG_FLAGSR_ERASEREADY(x) (((x) >> 7) & 1) 101 #define CAD_QSPI_STIG_FLAGSR_ERASEERROR(x) (((x) >> 5) & 1) 102 #define CAD_QSPI_STIG_FLAGSR_PROGRAMERROR(x) (((x) >> 4) & 1) 103 #define CAD_QSPI_STIG_OPCODE_CLFSR 0x50 104 #define CAD_QSPI_STIG_OPCODE_RDID 0x9f 105 #define CAD_QSPI_STIG_OPCODE_WRDIS 0x4 106 #define CAD_QSPI_STIG_OPCODE_WREN 0x6 107 #define CAD_QSPI_STIG_OPCODE_SUBSEC_ERASE 0x20 108 #define CAD_QSPI_STIG_OPCODE_SEC_ERASE 0xd8 109 #define CAD_QSPI_STIG_OPCODE_WREN_EXT_REG 0xc5 110 #define CAD_QSPI_STIG_OPCODE_DIE_ERASE 0xc4 111 #define CAD_QSPI_STIG_OPCODE_BULK_ERASE 0xc7 112 #define CAD_QSPI_STIG_OPCODE_RDSR 0x5 113 #define CAD_QSPI_STIG_OPCODE_RDFLGSR 0x70 114 #define CAD_QSPI_STIG_OPCODE_RESET_EN 0x66 115 #define CAD_QSPI_STIG_OPCODE_RESET_MEM 0x99 116 #define CAD_QSPI_STIG_RDID_CAPACITYID(x) (((x) >> 16) & 0xff) 117 #define CAD_QSPI_STIG_SR_BUSY(x) (((x) >> 0) & 1) 118 119 120 #define CAD_QSPI_INST_SINGLE 0 121 #define CAD_QSPI_INST_DUAL 1 122 #define CAD_QSPI_INST_QUAD 2 123 124 #define CAD_QSPI_INDRDSTADDR 0x68 125 #define CAD_QSPI_INDRDCNT 0x6c 126 #define CAD_QSPI_INDRD 0x60 127 #define CAD_QSPI_INDRD_RD_STAT(x) (((x) >> 2) & 1) 128 #define CAD_QSPI_INDRD_START 1 129 #define CAD_QSPI_INDRD_IND_OPS_DONE 0x20 130 131 #define CAD_QSPI_INDWR 0x70 132 #define CAD_QSPI_INDWR_RDSTAT(x) (((x) >> 2) & 1) 133 #define CAD_QSPI_INDWRSTADDR 0x78 134 #define CAD_QSPI_INDWRCNT 0x7c 135 #define CAD_QSPI_INDWR 0x70 136 #define CAD_QSPI_INDWR_START 0x1 137 #define CAD_QSPI_INDWR_INDDONE 0x20 138 139 #define CAD_QSPI_INT_STATUS_ALL 0x0000ffff 140 141 #define CAD_QSPI_N25Q_DIE_SIZE 0x02000000 142 #define CAD_QSPI_BANK_SIZE 0x01000000 143 #define CAD_QSPI_PAGE_SIZE 0x00000100 144 145 #define CAD_QSPI_IRQMSK 0x44 146 147 #define CAD_QSPI_SUBSECTOR_SIZE 0x1000 148 149 #define S10_QSPI_ADDR_BYTES 2 150 #define S10_QSPI_BYTES_PER_DEV 256 151 #define S10_BYTES_PER_BLOCK 16 152 153 #define QSPI_FAST_READ 0xb 154 155 // QSPI CONFIGURATIONS 156 157 #define QSPI_CONFIG_CPOL 1 158 #define QSPI_CONFIG_CPHA 1 159 160 #define QSPI_CONFIG_CSSOT 0x14 161 #define QSPI_CONFIG_CSEOT 0x14 162 #define QSPI_CONFIG_CSDADS 0xff 163 #define QSPI_CONFIG_CSDA 0xc8 164 165 int cad_qspi_init(uint32_t desired_clk_freq, uint32_t clk_phase, 166 uint32_t clk_pol, uint32_t csda, uint32_t csdads, 167 uint32_t cseot, uint32_t cssot, uint32_t rddatacap); 168 void cad_qspi_set_chip_select(int cs); 169 int cad_qspi_erase(uint32_t offset, uint32_t size); 170 int cad_qspi_write(void *buffer, uint32_t offset, uint32_t size); 171 int cad_qspi_read(void *buffer, uint32_t offset, uint32_t size); 172 int cad_qspi_update(void *buffer, uint32_t offset, uint32_t size); 173 174 #endif 175 176