1*ddaf02d1SJit Loon Lim /* 2*ddaf02d1SJit Loon Lim * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. 3*ddaf02d1SJit Loon Lim * 4*ddaf02d1SJit Loon Lim * SPDX-License-Identifier: BSD-3-Clause 5*ddaf02d1SJit Loon Lim */ 6*ddaf02d1SJit Loon Lim 7*ddaf02d1SJit Loon Lim #include <assert.h> 8*ddaf02d1SJit Loon Lim #include <errno.h> 9*ddaf02d1SJit Loon Lim #include <stdbool.h> 10*ddaf02d1SJit Loon Lim #include <string.h> 11*ddaf02d1SJit Loon Lim 12*ddaf02d1SJit Loon Lim #include <arch_helpers.h> 13*ddaf02d1SJit Loon Lim #include <common/debug.h> 14*ddaf02d1SJit Loon Lim #include <drivers/cadence/cdns_nand.h> 15*ddaf02d1SJit Loon Lim #include <drivers/delay_timer.h> 16*ddaf02d1SJit Loon Lim #include <lib/mmio.h> 17*ddaf02d1SJit Loon Lim #include <lib/utils.h> 18*ddaf02d1SJit Loon Lim #include "nand.h" 19*ddaf02d1SJit Loon Lim 20*ddaf02d1SJit Loon Lim #include "agilex5_pinmux.h" 21*ddaf02d1SJit Loon Lim #include "combophy/combophy.h" 22*ddaf02d1SJit Loon Lim 23*ddaf02d1SJit Loon Lim /* Pinmux configuration */ 24*ddaf02d1SJit Loon Lim static void nand_pinmux_config(void) 25*ddaf02d1SJit Loon Lim { 26*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN0SEL), SOCFPGA_PINMUX_SEL_NAND); 27*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN1SEL), SOCFPGA_PINMUX_SEL_NAND); 28*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN2SEL), SOCFPGA_PINMUX_SEL_NAND); 29*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN3SEL), SOCFPGA_PINMUX_SEL_NAND); 30*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN4SEL), SOCFPGA_PINMUX_SEL_NAND); 31*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN5SEL), SOCFPGA_PINMUX_SEL_NAND); 32*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN6SEL), SOCFPGA_PINMUX_SEL_NAND); 33*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN7SEL), SOCFPGA_PINMUX_SEL_NAND); 34*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN8SEL), SOCFPGA_PINMUX_SEL_NAND); 35*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN9SEL), SOCFPGA_PINMUX_SEL_NAND); 36*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN10SEL), SOCFPGA_PINMUX_SEL_NAND); 37*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN11SEL), SOCFPGA_PINMUX_SEL_NAND); 38*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN12SEL), SOCFPGA_PINMUX_SEL_NAND); 39*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN13SEL), SOCFPGA_PINMUX_SEL_NAND); 40*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN14SEL), SOCFPGA_PINMUX_SEL_NAND); 41*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN16SEL), SOCFPGA_PINMUX_SEL_NAND); 42*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN17SEL), SOCFPGA_PINMUX_SEL_NAND); 43*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN18SEL), SOCFPGA_PINMUX_SEL_NAND); 44*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN19SEL), SOCFPGA_PINMUX_SEL_NAND); 45*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN20SEL), SOCFPGA_PINMUX_SEL_NAND); 46*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN21SEL), SOCFPGA_PINMUX_SEL_NAND); 47*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN22SEL), SOCFPGA_PINMUX_SEL_NAND); 48*ddaf02d1SJit Loon Lim mmio_write_32(SOCFPGA_PINMUX(PIN23SEL), SOCFPGA_PINMUX_SEL_NAND); 49*ddaf02d1SJit Loon Lim } 50*ddaf02d1SJit Loon Lim 51*ddaf02d1SJit Loon Lim int nand_init(handoff *hoff_ptr) 52*ddaf02d1SJit Loon Lim { 53*ddaf02d1SJit Loon Lim /* NAND pin mux configuration */ 54*ddaf02d1SJit Loon Lim nand_pinmux_config(); 55*ddaf02d1SJit Loon Lim 56*ddaf02d1SJit Loon Lim return cdns_nand_host_init(); 57*ddaf02d1SJit Loon Lim } 58