1/* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <platform_def.h> 11#include <el3_common_macros.S> 12 13 .globl plat_secondary_cold_boot_setup 14 .globl platform_is_primary_cpu 15 .globl plat_is_my_cpu_primary 16 .globl plat_my_core_pos 17 .globl plat_crash_console_init 18 .globl plat_crash_console_putc 19 .globl plat_crash_console_flush 20 .globl platform_mem_init 21 .globl plat_secondary_cpus_bl31_entry 22 23 .globl plat_get_my_entrypoint 24 25 /* ----------------------------------------------------- 26 * void plat_secondary_cold_boot_setup (void); 27 * 28 * This function performs any platform specific actions 29 * needed for a secondary cpu after a cold reset e.g 30 * mark the cpu's presence, mechanism to place it in a 31 * holding pen etc. 32 * ----------------------------------------------------- 33 */ 34func plat_secondary_cold_boot_setup 35 /* Wait until the it gets reset signal from rstmgr gets populated */ 36poll_mailbox: 37 wfi 38 mov_imm x0, PLAT_SEC_ENTRY 39 ldr x1, [x0] 40 mov_imm x2, PLAT_CPUID_RELEASE 41 ldr x3, [x2] 42 mrs x4, mpidr_el1 43 and x4, x4, #0xff 44 cmp x3, x4 45 b.ne poll_mailbox 46 br x1 47endfunc plat_secondary_cold_boot_setup 48 49func platform_is_primary_cpu 50 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 51 cmp x0, #PLAT_PRIMARY_CPU 52 cset x0, eq 53 ret 54endfunc platform_is_primary_cpu 55 56func plat_is_my_cpu_primary 57 mrs x0, mpidr_el1 58 b platform_is_primary_cpu 59endfunc plat_is_my_cpu_primary 60 61func plat_my_core_pos 62 mrs x0, mpidr_el1 63 and x1, x0, #MPIDR_CPU_MASK 64 and x0, x0, #MPIDR_CLUSTER_MASK 65 add x0, x1, x0, LSR #6 66 ret 67endfunc plat_my_core_pos 68 69func plat_get_my_entrypoint 70 mov_imm x1, PLAT_SEC_ENTRY 71 ldr x0, [x1] 72 ret 73endfunc plat_get_my_entrypoint 74 75 /* --------------------------------------------- 76 * int plat_crash_console_init(void) 77 * Function to initialize the crash console 78 * without a C Runtime to print crash report. 79 * Clobber list : x0, x1, x2 80 * --------------------------------------------- 81 */ 82func plat_crash_console_init 83 mov_imm x0, PLAT_UART0_BASE 84 mov_imm x1, PLAT_UART_CLOCK 85 mov_imm x2, PLAT_BAUDRATE 86 b console_16550_core_init 87endfunc plat_crash_console_init 88 89 /* --------------------------------------------- 90 * int plat_crash_console_putc(void) 91 * Function to print a character on the crash 92 * console without a C Runtime. 93 * Clobber list : x1, x2 94 * --------------------------------------------- 95 */ 96func plat_crash_console_putc 97 mov_imm x1, PLAT_UART0_BASE 98 b console_16550_core_putc 99endfunc plat_crash_console_putc 100 101func plat_crash_console_flush 102 mov_imm x0, CRASH_CONSOLE_BASE 103 b console_16550_core_flush 104endfunc plat_crash_console_flush 105 106 107 /* -------------------------------------------------------- 108 * void platform_mem_init (void); 109 * 110 * Any memory init, relocation to be done before the 111 * platform boots. Called very early in the boot process. 112 * -------------------------------------------------------- 113 */ 114func platform_mem_init 115 mov x0, #0 116 ret 117endfunc platform_mem_init 118 119func plat_secondary_cpus_bl31_entry 120 el3_entrypoint_common \ 121 _init_sctlr=0 \ 122 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 123 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 124 _init_memory=1 \ 125 _init_c_runtime=1 \ 126 _exception_vectors=runtime_exceptions \ 127 _pie_fixup_size=BL31_LIMIT - BL31_BASE 128endfunc plat_secondary_cpus_bl31_entry 129