1*3f7b1490SHadi Asyrafi/* 2*3f7b1490SHadi Asyrafi * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*3f7b1490SHadi Asyrafi * 4*3f7b1490SHadi Asyrafi * SPDX-License-Identifier: BSD-3-Clause 5*3f7b1490SHadi Asyrafi */ 6*3f7b1490SHadi Asyrafi 7*3f7b1490SHadi Asyrafi#include <arch.h> 8*3f7b1490SHadi Asyrafi#include <asm_macros.S> 9*3f7b1490SHadi Asyrafi#include <cpu_macros.S> 10*3f7b1490SHadi Asyrafi#include <platform_def.h> 11*3f7b1490SHadi Asyrafi 12*3f7b1490SHadi Asyrafi .globl plat_secondary_cold_boot_setup 13*3f7b1490SHadi Asyrafi .globl platform_is_primary_cpu 14*3f7b1490SHadi Asyrafi .globl plat_is_my_cpu_primary 15*3f7b1490SHadi Asyrafi .globl plat_my_core_pos 16*3f7b1490SHadi Asyrafi .globl plat_crash_console_init 17*3f7b1490SHadi Asyrafi .globl plat_crash_console_putc 18*3f7b1490SHadi Asyrafi .globl plat_crash_console_flush 19*3f7b1490SHadi Asyrafi .globl platform_mem_init 20*3f7b1490SHadi Asyrafi 21*3f7b1490SHadi Asyrafi .globl plat_get_my_entrypoint 22*3f7b1490SHadi Asyrafi 23*3f7b1490SHadi Asyrafi /* ----------------------------------------------------- 24*3f7b1490SHadi Asyrafi * void plat_secondary_cold_boot_setup (void); 25*3f7b1490SHadi Asyrafi * 26*3f7b1490SHadi Asyrafi * This function performs any platform specific actions 27*3f7b1490SHadi Asyrafi * needed for a secondary cpu after a cold reset e.g 28*3f7b1490SHadi Asyrafi * mark the cpu's presence, mechanism to place it in a 29*3f7b1490SHadi Asyrafi * holding pen etc. 30*3f7b1490SHadi Asyrafi * ----------------------------------------------------- 31*3f7b1490SHadi Asyrafi */ 32*3f7b1490SHadi Asyrafifunc plat_secondary_cold_boot_setup 33*3f7b1490SHadi Asyrafi /* Wait until the it gets reset signal from rstmgr gets populated */ 34*3f7b1490SHadi Asyrafipoll_mailbox: 35*3f7b1490SHadi Asyrafi wfi 36*3f7b1490SHadi Asyrafi 37*3f7b1490SHadi Asyrafi mov_imm x0, PLAT_SEC_ENTRY 38*3f7b1490SHadi Asyrafi ldr x1, [x0] 39*3f7b1490SHadi Asyrafi mov_imm x2, PLAT_CPUID_RELEASE 40*3f7b1490SHadi Asyrafi ldr x3, [x2] 41*3f7b1490SHadi Asyrafi mrs x4, mpidr_el1 42*3f7b1490SHadi Asyrafi and x4, x4, #0xff 43*3f7b1490SHadi Asyrafi cmp x3, x4 44*3f7b1490SHadi Asyrafi b.ne poll_mailbox 45*3f7b1490SHadi Asyrafi br x1 46*3f7b1490SHadi Asyrafiendfunc plat_secondary_cold_boot_setup 47*3f7b1490SHadi Asyrafi 48*3f7b1490SHadi Asyrafifunc platform_is_primary_cpu 49*3f7b1490SHadi Asyrafi and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 50*3f7b1490SHadi Asyrafi cmp x0, #PLAT_PRIMARY_CPU 51*3f7b1490SHadi Asyrafi cset x0, eq 52*3f7b1490SHadi Asyrafi ret 53*3f7b1490SHadi Asyrafiendfunc platform_is_primary_cpu 54*3f7b1490SHadi Asyrafi 55*3f7b1490SHadi Asyrafifunc plat_is_my_cpu_primary 56*3f7b1490SHadi Asyrafi mrs x0, mpidr_el1 57*3f7b1490SHadi Asyrafi b platform_is_primary_cpu 58*3f7b1490SHadi Asyrafiendfunc plat_is_my_cpu_primary 59*3f7b1490SHadi Asyrafi 60*3f7b1490SHadi Asyrafifunc plat_my_core_pos 61*3f7b1490SHadi Asyrafi mrs x0, mpidr_el1 62*3f7b1490SHadi Asyrafi and x1, x0, #MPIDR_CPU_MASK 63*3f7b1490SHadi Asyrafi and x0, x0, #MPIDR_CLUSTER_MASK 64*3f7b1490SHadi Asyrafi add x0, x1, x0, LSR #6 65*3f7b1490SHadi Asyrafi ret 66*3f7b1490SHadi Asyrafiendfunc plat_my_core_pos 67*3f7b1490SHadi Asyrafi 68*3f7b1490SHadi Asyrafifunc plat_get_my_entrypoint 69*3f7b1490SHadi Asyrafi mov_imm x1, PLAT_SEC_ENTRY 70*3f7b1490SHadi Asyrafi ldr x0, [x1] 71*3f7b1490SHadi Asyrafi ret 72*3f7b1490SHadi Asyrafiendfunc plat_get_my_entrypoint 73*3f7b1490SHadi Asyrafi 74*3f7b1490SHadi Asyrafi /* --------------------------------------------- 75*3f7b1490SHadi Asyrafi * int plat_crash_console_init(void) 76*3f7b1490SHadi Asyrafi * Function to initialize the crash console 77*3f7b1490SHadi Asyrafi * without a C Runtime to print crash report. 78*3f7b1490SHadi Asyrafi * Clobber list : x0, x1, x2 79*3f7b1490SHadi Asyrafi * --------------------------------------------- 80*3f7b1490SHadi Asyrafi */ 81*3f7b1490SHadi Asyrafifunc plat_crash_console_init 82*3f7b1490SHadi Asyrafi mov_imm x0, PLAT_UART0_BASE 83*3f7b1490SHadi Asyrafi mov_imm x1, PLAT_UART_CLOCK 84*3f7b1490SHadi Asyrafi mov_imm x2, PLAT_BAUDRATE 85*3f7b1490SHadi Asyrafi b console_16550_core_init 86*3f7b1490SHadi Asyrafiendfunc plat_crash_console_init 87*3f7b1490SHadi Asyrafi 88*3f7b1490SHadi Asyrafi /* --------------------------------------------- 89*3f7b1490SHadi Asyrafi * int plat_crash_console_putc(void) 90*3f7b1490SHadi Asyrafi * Function to print a character on the crash 91*3f7b1490SHadi Asyrafi * console without a C Runtime. 92*3f7b1490SHadi Asyrafi * Clobber list : x1, x2 93*3f7b1490SHadi Asyrafi * --------------------------------------------- 94*3f7b1490SHadi Asyrafi */ 95*3f7b1490SHadi Asyrafifunc plat_crash_console_putc 96*3f7b1490SHadi Asyrafi mov_imm x1, PLAT_UART0_BASE 97*3f7b1490SHadi Asyrafi b console_16550_core_putc 98*3f7b1490SHadi Asyrafiendfunc plat_crash_console_putc 99*3f7b1490SHadi Asyrafi 100*3f7b1490SHadi Asyrafifunc plat_crash_console_flush 101*3f7b1490SHadi Asyrafi mov_imm x0, CRASH_CONSOLE_BASE 102*3f7b1490SHadi Asyrafi b console_16550_core_flush 103*3f7b1490SHadi Asyrafiendfunc plat_crash_console_flush 104*3f7b1490SHadi Asyrafi 105*3f7b1490SHadi Asyrafi 106*3f7b1490SHadi Asyrafi /* -------------------------------------------------------- 107*3f7b1490SHadi Asyrafi * void platform_mem_init (void); 108*3f7b1490SHadi Asyrafi * 109*3f7b1490SHadi Asyrafi * Any memory init, relocation to be done before the 110*3f7b1490SHadi Asyrafi * platform boots. Called very early in the boot process. 111*3f7b1490SHadi Asyrafi * -------------------------------------------------------- 112*3f7b1490SHadi Asyrafi */ 113*3f7b1490SHadi Asyrafifunc platform_mem_init 114*3f7b1490SHadi Asyrafi mov x0, #0 115*3f7b1490SHadi Asyrafi ret 116*3f7b1490SHadi Asyrafiendfunc platform_mem_init 117