1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLAT_SOCFPGA_DEF_H 10 #define PLAT_SOCFPGA_DEF_H 11 12 #include "agilex5_memory_controller.h" 13 #include "agilex5_system_manager.h" 14 15 #include <platform_def.h> 16 17 /* Platform Setting */ 18 #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5 19 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 20 /* 1 = Flush cache, 0 = No cache flush. 21 * Default for Agilex5 is Cache flush. 22 */ 23 #define CACHE_FLUSH 1 24 #define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */ 25 #define XLAT_TABLES_V2 U(1) 26 #define PLAT_PRIMARY_CPU_A55 0x000 27 #define PLAT_PRIMARY_CPU_A76 0x200 28 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT 29 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 30 #define PLAT_L2_RESET_REQ 0xB007C0DE 31 #define PLAT_TIMER_BASE_ADDR 0x10D01000 32 33 /* System Counter */ 34 /* TODO: Update back to 400MHz. 35 * This shall be updated to read from L4 clock instead of hardcoded. 36 */ 37 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS U(400000000) 38 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400) 39 40 /* FPGA config helpers */ 41 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x80400000 42 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x82000000 43 44 /* QSPI Setting */ 45 #define CAD_QSPIDATA_OFST 0x10900000 46 #define CAD_QSPI_OFFSET 0x108d2000 47 48 /* SDMMC Setting */ 49 # if ARM_LINUX_KERNEL_AS_BL33 50 #define SOCFPGA_MMC_BLOCK_SIZE U(32768) 51 # else 52 #define SOCFPGA_MMC_BLOCK_SIZE U(8192) 53 # endif 54 55 /* Register Mapping */ 56 #define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000 57 #define SOCFPGA_F2SDRAMMGR_REG_BASE 0x18001000 58 59 #define SOCFPGA_MMC_REG_BASE 0x10808000 60 #define SOCFPGA_MEMCTRL_REG_BASE 0x108CC000 61 #define SOCFPGA_RSTMGR_REG_BASE 0x10d11000 62 #define SOCFPGA_SYSMGR_REG_BASE 0x10d12000 63 #define SOCFPGA_PINMUX_REG_BASE 0x10d13000 64 #define SOCFPGA_NAND_REG_BASE 0x10B80000 65 #define SOCFPGA_ECC_QSPI_REG_BASE 0x10A22000 66 67 #define SOCFPGA_L4_PER_SCR_REG_BASE 0x10d21000 68 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100 69 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0x10d21200 70 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300 71 72 /* Define maximum page size for NAND flash devices */ 73 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x2000) 74 75 /******************************************************************************* 76 * Platform memory map related constants 77 ******************************************************************************/ 78 #define DRAM_BASE (0x80000000) 79 #define DRAM_SIZE (0x80000000) 80 81 #define OCRAM_BASE (0x00000000) 82 #define OCRAM_SIZE (0x00080000) 83 84 #define MEM64_BASE (0x0080000000) 85 #define MEM64_SIZE (0x0080000000) 86 87 //128MB PSS 88 #define PSS_BASE (0x10000000) 89 #define PSS_SIZE (0x08000000) 90 91 //64MB MPFE 92 #define MPFE_BASE (0x18000000) 93 #define MPFE_SIZE (0x04000000) 94 95 //16MB CCU 96 #define CCU_BASE (0x1C000000) 97 #define CCU_SIZE (0x01000000) 98 99 //1MB GIC 100 #define GIC_BASE (0x1D000000) 101 #define GIC_SIZE (0x00100000) 102 103 #define BL2_BASE (0x00000000) 104 #define BL2_LIMIT (0x0007E000) 105 106 #define BL31_BASE (0x80000000) 107 #define BL31_LIMIT (0x82000000) 108 /******************************************************************************* 109 * UART related constants 110 ******************************************************************************/ 111 #define PLAT_UART0_BASE (0x10C02000) 112 #define PLAT_UART1_BASE (0x10C02100) 113 114 /******************************************************************************* 115 * WDT related constants 116 ******************************************************************************/ 117 #define WDT_BASE (0x10D00200) 118 119 /******************************************************************************* 120 * GIC related constants 121 ******************************************************************************/ 122 #define PLAT_GIC_BASE (0x1D000000) 123 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x20000) 124 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x00000) 125 #define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x60000) 126 127 #define PLAT_INTEL_SOCFPGA_GICR_BASE PLAT_GICR_BASE 128 129 /******************************************************************************* 130 * SDMMC related pointer function 131 ******************************************************************************/ 132 #define SDMMC_READ_BLOCKS sdmmc_read_blocks 133 #define SDMMC_WRITE_BLOCKS sdmmc_write_blocks 134 135 /******************************************************************************* 136 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 137 * is done and HPS should trigger warm reset via RMR_EL3. 138 ******************************************************************************/ 139 #define L2_RESET_DONE_REG 0x10D12218 140 141 #endif /* PLAT_SOCFPGA_DEF_H */ 142