1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLAT_SOCFPGA_DEF_H 10 #define PLAT_SOCFPGA_DEF_H 11 12 #include "agilex5_memory_controller.h" 13 #include "agilex5_system_manager.h" 14 15 #include <platform_def.h> 16 17 /* Platform Setting */ 18 #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5 19 /* 1 = Flush cache, 0 = No cache flush. 20 * Default for Agilex5 is Cache flush. 21 */ 22 #define CACHE_FLUSH 1 23 #define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */ 24 #define XLAT_TABLES_V2 U(1) 25 #define PLAT_PRIMARY_CPU_A55 0x000 26 #define PLAT_PRIMARY_CPU_A76 0x200 27 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT 28 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 29 #define PLAT_L2_RESET_REQ 0xB007C0DE 30 #define PLAT_HANDOFF_OFFSET 0x0007F000 31 #define PLAT_TIMER_BASE_ADDR 0x10D01000 32 #define SOCFPGA_DTB_BASE 0x80020000 33 #define DT_COMPATIBLE_STR "arm,altera socfpga-agilex5" 34 35 /* System Counter */ 36 /* TODO: Update back to 400MHz. 37 * This shall be updated to read from L4 clock instead of hardcoded. 38 */ 39 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS U(400000000) 40 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400) 41 42 /* FPGA config helpers */ 43 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x80400000 44 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x82000000 45 46 /* QSPI Setting */ 47 #define CAD_QSPIDATA_OFST 0x10900000 48 #define CAD_QSPI_OFFSET 0x108d2000 49 50 /* FIP Setting */ 51 #define PLAT_FIP_BASE (0) 52 #if ARM_LINUX_KERNEL_AS_BL33 53 #define PLAT_FIP_MAX_SIZE (0x8000000) 54 #else 55 #define PLAT_FIP_MAX_SIZE (0x1000000) 56 #endif 57 58 /* SDMMC Setting */ 59 #if ARM_LINUX_KERNEL_AS_BL33 60 #define PLAT_MMC_DATA_BASE (0x90000000) 61 #define PLAT_MMC_DATA_SIZE (0x100000) 62 #define SOCFPGA_MMC_BLOCK_SIZE U(32768) 63 #else 64 #define PLAT_MMC_DATA_BASE (0x0007D000) 65 #define PLAT_MMC_DATA_SIZE (0x2000) 66 #define SOCFPGA_MMC_BLOCK_SIZE U(8192) 67 #endif 68 69 /* Register Mapping */ 70 #define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000 71 #define SOCFPGA_F2SDRAMMGR_REG_BASE 0x18001000 72 73 #define SOCFPGA_MMC_REG_BASE 0x10808000 74 #define SOCFPGA_MEMCTRL_REG_BASE 0x108CC000 75 #define SOCFPGA_RSTMGR_REG_BASE 0x10d11000 76 #define SOCFPGA_SYSMGR_REG_BASE 0x10d12000 77 #define SOCFPGA_PINMUX_REG_BASE 0x10d13000 78 #define SOCFPGA_NAND_REG_BASE 0x10B80000 79 #define SOCFPGA_ECC_QSPI_REG_BASE 0x10A22000 80 81 #define SOCFPGA_L4_PER_SCR_REG_BASE 0x10d21000 82 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100 83 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0x10d21200 84 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300 85 #define SOCFPGA_SDMMC_SECU_BIT 0x40 86 #define SOCFPGA_LWSOC2FPGA_ENABLE 0xffe0301 87 #define SOCFPGA_SDMMC_SECU_BIT_ENABLE 0x1010001 88 89 90 /* Define maximum page size for NAND flash devices */ 91 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x2000) 92 93 /* OCRAM Register*/ 94 95 #define OCRAM_REG_BASE 0x108CC400 96 #define OCRAM_REGION_0_OFFSET 0x18 97 #define OCRAM_REGION_0_REG_BASE (OCRAM_REG_BASE + \ 98 OCRAM_REGION_0_OFFSET) 99 #define OCRAM_NON_SECURE_ENABLE 0x0 100 101 102 /* 103 * Magic key bits: 4 bits[5:2] from boot scratch register COLD3 are used to 104 * indicate the below requests/status 105 * 0x0 : Default value on reset, not used 106 * 0x1 : L2/warm reset is completed 107 * 0x2 : SMP secondary core boot requests 108 * 0x3 - 0xF : Reserved for future use 109 */ 110 #define BS_REG_MAGIC_KEYS_MASK 0x3C 111 #define BS_REG_MAGIC_KEYS_POS 0x02 112 #define L2_RESET_DONE_STATUS (0x01 << BS_REG_MAGIC_KEYS_POS) 113 #define SMP_SEC_CORE_BOOT_REQ (0x02 << BS_REG_MAGIC_KEYS_POS) 114 #define ALIGN_CHECK_64BIT_MASK 0x07 115 116 /******************************************************************************* 117 * Platform memory map related constants 118 ******************************************************************************/ 119 #define DRAM_BASE (0x80000000) 120 #define DRAM_SIZE (0x80000000) 121 122 #define OCRAM_BASE (0x00000000) 123 #define OCRAM_SIZE (0x00080000) 124 125 #define MEM64_BASE (0x0080000000) 126 #define MEM64_SIZE (0x0080000000) 127 128 //128MB PSS 129 #define PSS_BASE (0x10000000) 130 #define PSS_SIZE (0x08000000) 131 132 //64MB MPFE 133 #define MPFE_BASE (0x18000000) 134 #define MPFE_SIZE (0x04000000) 135 136 //16MB CCU 137 #define CCU_BASE (0x1C000000) 138 #define CCU_SIZE (0x01000000) 139 140 //1MB GIC 141 #define GIC_BASE (0x1D000000) 142 #define GIC_SIZE (0x00100000) 143 144 #define BL2_BASE (0x00000000) 145 #define BL2_LIMIT (0x0007E000) 146 147 #define BL31_BASE (0x80000000) 148 #define BL31_LIMIT (0x82000000) 149 /******************************************************************************* 150 * UART related constants 151 ******************************************************************************/ 152 #define PLAT_UART0_BASE (0x10C02000) 153 #define PLAT_UART1_BASE (0x10C02100) 154 155 /******************************************************************************* 156 * WDT related constants 157 ******************************************************************************/ 158 #define WDT_BASE (0x10D00200) 159 160 /******************************************************************************* 161 * GIC related constants 162 ******************************************************************************/ 163 #define PLAT_GIC_BASE (0x1D000000) 164 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x20000) 165 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x00000) 166 #define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x60000) 167 168 #define PLAT_INTEL_SOCFPGA_GICR_BASE PLAT_GICR_BASE 169 170 /******************************************************************************* 171 * SDMMC related pointer function 172 ******************************************************************************/ 173 #define SDMMC_READ_BLOCKS sdmmc_read_blocks 174 #define SDMMC_WRITE_BLOCKS sdmmc_write_blocks 175 176 /******************************************************************************* 177 * sysmgr.boot_scratch_cold3 bits[5:2] are used to indicate L2 reset 178 * is done, or SMP secondary cores boot request status. 179 ******************************************************************************/ 180 #define L2_RESET_DONE_REG SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_3) 181 182 #endif /* PLAT_SOCFPGA_DEF_H */ 183