xref: /rk3399_ARM-atf/plat/intel/soc/agilex5/include/agilex5_ddr.h (revision ce21a1a909f2ec98f83c25dd2ed3b7fedd46c46b)
1*ce21a1a9SSieu Mun Tang /*
2*ce21a1a9SSieu Mun Tang  * Copyright (c) 2024, Altera Corporation. All rights reserved.
3*ce21a1a9SSieu Mun Tang  *
4*ce21a1a9SSieu Mun Tang  * SPDX-License-Identifier: BSD-3-Clause
5*ce21a1a9SSieu Mun Tang  */
6*ce21a1a9SSieu Mun Tang 
7*ce21a1a9SSieu Mun Tang #ifndef AGILEX5_DDR_H
8*ce21a1a9SSieu Mun Tang #define AGILEX5_DDR_H
9*ce21a1a9SSieu Mun Tang 
10*ce21a1a9SSieu Mun Tang #include <stdint.h>
11*ce21a1a9SSieu Mun Tang #include <stdio.h>
12*ce21a1a9SSieu Mun Tang #include <string.h>
13*ce21a1a9SSieu Mun Tang #include <lib/utils_def.h>
14*ce21a1a9SSieu Mun Tang 
15*ce21a1a9SSieu Mun Tang #include "socfpga_handoff.h"
16*ce21a1a9SSieu Mun Tang 
17*ce21a1a9SSieu Mun Tang #define CONFIG_NR_DRAM_BANKS	1
18*ce21a1a9SSieu Mun Tang 
19*ce21a1a9SSieu Mun Tang typedef unsigned long long phys_addr_t;
20*ce21a1a9SSieu Mun Tang typedef unsigned long long phys_size_t;
21*ce21a1a9SSieu Mun Tang typedef phys_addr_t fdt_addr_t;
22*ce21a1a9SSieu Mun Tang 
23*ce21a1a9SSieu Mun Tang /* DDR/RAM configuration */
24*ce21a1a9SSieu Mun Tang struct ddr_info {
25*ce21a1a9SSieu Mun Tang 	phys_addr_t start;
26*ce21a1a9SSieu Mun Tang 	phys_size_t size;
27*ce21a1a9SSieu Mun Tang };
28*ce21a1a9SSieu Mun Tang 
29*ce21a1a9SSieu Mun Tang int agilex5_ddr_init(handoff *hoff_ptr);
30*ce21a1a9SSieu Mun Tang 
31*ce21a1a9SSieu Mun Tang #endif /* AGILEX5_DDR_H */
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