1 /* 2 * Copyright (c) 2019-2024, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <drivers/arm/gic_common.h> 14 #include <drivers/arm/gicv3.h> 15 #include <drivers/ti/uart/uart_16550.h> 16 #include <lib/mmio.h> 17 #include <lib/xlat_tables/xlat_mmu_helpers.h> 18 #include <lib/xlat_tables/xlat_tables_v2.h> 19 #include <plat/common/platform.h> 20 21 #include "agilex5_cache.h" 22 #include "agilex5_power_manager.h" 23 #include "ccu/ncore_ccu.h" 24 #include "socfpga_dt.h" 25 #include "socfpga_mailbox.h" 26 #include "socfpga_private.h" 27 #include "socfpga_reset_manager.h" 28 29 /* Get non-secure SPSR for BL33. Zephyr and Linux */ 30 uint32_t arm_get_spsr_for_bl33_entry(void); 31 32 static entry_point_info_t bl32_image_ep_info; 33 static entry_point_info_t bl33_image_ep_info; 34 35 /* The GICv3 driver only needs to be initialized in EL3 */ 36 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 37 38 #define SMMU_SDMMC 39 40 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 41 { 42 entry_point_info_t *next_image_info; 43 44 next_image_info = (type == NON_SECURE) ? 45 &bl33_image_ep_info : &bl32_image_ep_info; 46 47 /* None of the images on this platform can have 0x0 as the entrypoint */ 48 if (next_image_info->pc) 49 return next_image_info; 50 else 51 return NULL; 52 } 53 54 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 55 u_register_t arg2, u_register_t arg3) 56 { 57 static console_t console; 58 59 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); 60 61 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, 62 PLAT_BAUDRATE, &console); 63 64 setup_smmu_stream_id(); 65 66 /* 67 * Check params passed from BL31 should not be NULL, 68 */ 69 void *from_bl2 = (void *) arg0; 70 71 #if RESET_TO_BL31 72 /* There are no parameters from BL2 if BL31 is a reset vector */ 73 assert(from_bl2 == NULL); 74 void *plat_params_from_bl2 = (void *) arg3; 75 76 assert(plat_params_from_bl2 == NULL); 77 78 /* Populate entry point information for BL33 */ 79 SET_PARAM_HEAD(&bl33_image_ep_info, 80 PARAM_EP, 81 VERSION_1, 82 0); 83 84 # if ARM_LINUX_KERNEL_AS_BL33 85 /* 86 * According to the file ``Documentation/arm64/booting.txt`` of the 87 * Linux kernel tree, Linux expects the physical address of the device 88 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 89 * must be 0. 90 */ 91 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 92 bl33_image_ep_info.args.arg1 = 0U; 93 bl33_image_ep_info.args.arg2 = 0U; 94 bl33_image_ep_info.args.arg3 = 0U; 95 # endif 96 97 #else /* RESET_TO_BL31 */ 98 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 99 100 assert(params_from_bl2 != NULL); 101 102 /* 103 * Copy BL32 (if populated by BL31) and BL33 entry point information. 104 * They are stored in Secure RAM, in BL31's address space. 105 */ 106 107 if (params_from_bl2->h.type == PARAM_BL_PARAMS && 108 params_from_bl2->h.version >= VERSION_2) { 109 110 bl_params_node_t *bl_params = params_from_bl2->head; 111 112 while (bl_params) { 113 if (bl_params->image_id == BL33_IMAGE_ID) { 114 bl33_image_ep_info = *bl_params->ep_info; 115 } 116 bl_params = bl_params->next_params_info; 117 } 118 } else { 119 struct socfpga_bl31_params *arg_from_bl2 = 120 (struct socfpga_bl31_params *) from_bl2; 121 122 assert(arg_from_bl2->h.type == PARAM_BL31); 123 assert(arg_from_bl2->h.version >= VERSION_1); 124 125 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 126 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 127 } 128 129 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 130 bl33_image_ep_info.args.arg1 = 0U; 131 bl33_image_ep_info.args.arg2 = 0U; 132 bl33_image_ep_info.args.arg3 = 0U; 133 #endif 134 135 /* 136 * Tell BL31 where the non-trusted software image 137 * is located and the entry state information 138 */ 139 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 140 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 141 142 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 143 } 144 145 static const interrupt_prop_t agx5_interrupt_props[] = { 146 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(INTR_GROUP1S), 147 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(INTR_GROUP0) 148 }; 149 150 gicv3_driver_data_t plat_gicv3_gic_data = { 151 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, 152 .gicr_base = PLAT_INTEL_SOCFPGA_GICR_BASE, 153 .interrupt_props = agx5_interrupt_props, 154 .interrupt_props_num = ARRAY_SIZE(agx5_interrupt_props), 155 .rdistif_num = PLATFORM_CORE_COUNT, 156 .rdistif_base_addrs = rdistif_base_addrs, 157 }; 158 159 /******************************************************************************* 160 * Perform any BL3-1 platform setup code 161 ******************************************************************************/ 162 void bl31_platform_setup(void) 163 { 164 socfpga_delay_timer_init(); 165 166 /* TODO: DTB not available */ 167 // socfpga_dt_populate_gicv3_config(SOCFPGA_DTB_BASE, &plat_gicv3_gic_data); 168 // NOTICE("SOCFPGA: GIC GICD base address 0x%lx\n", plat_gicv3_gic_data.gicd_base); 169 // NOTICE("SOCFPGA: GIC GICR base address 0x%lx\n", plat_gicv3_gic_data.gicr_base); 170 171 /* Initialize the gic cpu and distributor interfaces */ 172 gicv3_driver_init(&plat_gicv3_gic_data); 173 gicv3_distif_init(); 174 gicv3_rdistif_init(plat_my_core_pos()); 175 gicv3_cpuif_enable(plat_my_core_pos()); 176 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); 177 } 178 179 const mmap_region_t plat_agilex_mmap[] = { 180 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), 181 MAP_REGION_FLAT(PSS_BASE, PSS_SIZE, MT_DEVICE | MT_RW | MT_NS), 182 MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 183 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, MT_NON_CACHEABLE | MT_RW | MT_SECURE), 184 MAP_REGION_FLAT(CCU_BASE, CCU_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 185 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS), 186 MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 187 {0} 188 }; 189 190 /******************************************************************************* 191 * Perform the very early platform specific architectural setup here. At the 192 * moment this is only initializes the mmu in a quick and dirty way. 193 ******************************************************************************/ 194 void bl31_plat_arch_setup(void) 195 { 196 uint32_t boot_core = 0x00; 197 uint32_t cpuid = 0x00; 198 199 cpuid = MPIDR_AFFLVL1_VAL(read_mpidr()); 200 boot_core = ((mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00) >> 10); 201 NOTICE("SOCFPGA: Boot Core = %x\n", boot_core); 202 NOTICE("SOCFPGA: CPU ID = %x\n", cpuid); 203 INFO("SOCFPGA: Invalidate Data cache\n"); 204 invalidate_dcache_all(); 205 206 /* Invalidate for NS EL2 and EL1 */ 207 invalidate_cache_low_el(); 208 } 209 210 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */ 211 uintptr_t plat_get_ns_image_entrypoint(void) 212 { 213 #ifdef PRELOADED_BL33_BASE 214 return PRELOADED_BL33_BASE; 215 #else 216 return PLAT_NS_IMAGE_OFFSET; 217 #endif 218 } 219 220 /* Get non-secure SPSR for BL33. Zephyr and Linux */ 221 uint32_t arm_get_spsr_for_bl33_entry(void) 222 { 223 unsigned int mode; 224 uint32_t spsr; 225 226 /* Figure out what mode we enter the non-secure world in */ 227 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 228 229 /* 230 * TODO: Consider the possibility of specifying the SPSR in 231 * the FIP ToC and allowing the platform to have a say as 232 * well. 233 */ 234 spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 235 return spsr; 236 } 237 238 /* SMP: Secondary cores BL31 setup reset vector */ 239 void bl31_plat_set_secondary_cpu_entrypoint(unsigned int cpu_id) 240 { 241 unsigned int pch_cpu = 0x00; 242 unsigned int pchctlr_old = 0x00; 243 unsigned int pchctlr_new = 0x00; 244 uint32_t boot_core = 0x00; 245 246 /* Set bit for SMP secondary cores boot */ 247 mmio_clrsetbits_32(L2_RESET_DONE_REG, BS_REG_MAGIC_KEYS_MASK, 248 SMP_SEC_CORE_BOOT_REQ); 249 boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00); 250 /* Update the p-channel based on cpu id */ 251 pch_cpu = 1 << cpu_id; 252 253 if (boot_core == 0x00) { 254 /* Update reset vector to 0x00 */ 255 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU2, 256 (uint64_t) plat_secondary_cpus_bl31_entry >> 2); 257 } else { 258 /* Update reset vector to 0x00 */ 259 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU0, 260 (uint64_t) plat_secondary_cpus_bl31_entry >> 2); 261 } 262 263 /* Update reset vector to 0x00 */ 264 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU1, (uint64_t) plat_secondary_cpus_bl31_entry >> 2); 265 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU3, (uint64_t) plat_secondary_cpus_bl31_entry >> 2); 266 267 /* On all cores - temporary */ 268 pchctlr_old = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR)); 269 pchctlr_new = pchctlr_old | (pch_cpu<<1); 270 mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pchctlr_new); 271 272 /* We will only release the target secondary CPUs */ 273 /* Bit mask for each CPU BIT0-3 */ 274 mmio_write_32(RSTMGR_CPUSTRELEASE_CPUx, pch_cpu); 275 } 276 277 void bl31_plat_set_secondary_cpu_off(void) 278 { 279 unsigned int pch_cpu = 0x00; 280 unsigned int pch_cpu_off = 0x00; 281 unsigned int cpu_id = plat_my_core_pos(); 282 283 pch_cpu_off = 1 << cpu_id; 284 285 pch_cpu = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR)); 286 pch_cpu = pch_cpu & ~(pch_cpu_off << 1); 287 288 mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pch_cpu); 289 } 290 291 void bl31_plat_runtime_setup(void) 292 { 293 console_switch_state(CONSOLE_FLAG_RUNTIME|CONSOLE_FLAG_BOOT); 294 } 295 296 void bl31_plat_enable_mmu(uint32_t flags) 297 { 298 /* TODO: Enable mmu when needed */ 299 } 300