1 /* 2 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <drivers/arm/gic_common.h> 13 #include <drivers/arm/gicv3.h> 14 #include <drivers/ti/uart/uart_16550.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_mmu_helpers.h> 17 #include <lib/xlat_tables/xlat_tables_v2.h> 18 #include <plat/common/platform.h> 19 20 #include "agilex5_power_manager.h" 21 #include "ccu/ncore_ccu.h" 22 #include "socfpga_mailbox.h" 23 #include "socfpga_private.h" 24 #include "socfpga_reset_manager.h" 25 26 /* Get non-secure SPSR for BL33. Zephyr and Linux */ 27 uint32_t arm_get_spsr_for_bl33_entry(void); 28 29 static entry_point_info_t bl32_image_ep_info; 30 static entry_point_info_t bl33_image_ep_info; 31 32 /* The GICv3 driver only needs to be initialized in EL3 */ 33 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 34 35 #define SMMU_SDMMC 36 37 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 38 { 39 entry_point_info_t *next_image_info; 40 41 next_image_info = (type == NON_SECURE) ? 42 &bl33_image_ep_info : &bl32_image_ep_info; 43 44 /* None of the images on this platform can have 0x0 as the entrypoint */ 45 if (next_image_info->pc) 46 return next_image_info; 47 else 48 return NULL; 49 } 50 51 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 52 u_register_t arg2, u_register_t arg3) 53 { 54 static console_t console; 55 56 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); 57 58 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, 59 PLAT_BAUDRATE, &console); 60 61 init_ncore_ccu(); 62 setup_smmu_stream_id(); 63 64 /* 65 * Check params passed from BL31 should not be NULL, 66 */ 67 void *from_bl2 = (void *) arg0; 68 69 #if RESET_TO_BL31 70 /* There are no parameters from BL2 if BL31 is a reset vector */ 71 assert(from_bl2 == NULL); 72 void *plat_params_from_bl2 = (void *) arg3; 73 74 assert(plat_params_from_bl2 == NULL); 75 76 /* Populate entry point information for BL33 */ 77 SET_PARAM_HEAD(&bl33_image_ep_info, 78 PARAM_EP, 79 VERSION_1, 80 0); 81 82 # if ARM_LINUX_KERNEL_AS_BL33 83 /* 84 * According to the file ``Documentation/arm64/booting.txt`` of the 85 * Linux kernel tree, Linux expects the physical address of the device 86 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 87 * must be 0. 88 */ 89 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 90 bl33_image_ep_info.args.arg1 = 0U; 91 bl33_image_ep_info.args.arg2 = 0U; 92 bl33_image_ep_info.args.arg3 = 0U; 93 # endif 94 95 #else /* RESET_TO_BL31 */ 96 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 97 98 assert(params_from_bl2 != NULL); 99 100 /* 101 * Copy BL32 (if populated by BL31) and BL33 entry point information. 102 * They are stored in Secure RAM, in BL31's address space. 103 */ 104 105 if (params_from_bl2->h.type == PARAM_BL_PARAMS && 106 params_from_bl2->h.version >= VERSION_2) { 107 108 bl_params_node_t *bl_params = params_from_bl2->head; 109 110 while (bl_params) { 111 if (bl_params->image_id == BL33_IMAGE_ID) { 112 bl33_image_ep_info = *bl_params->ep_info; 113 } 114 bl_params = bl_params->next_params_info; 115 } 116 } else { 117 struct socfpga_bl31_params *arg_from_bl2 = 118 (struct socfpga_bl31_params *) from_bl2; 119 120 assert(arg_from_bl2->h.type == PARAM_BL31); 121 assert(arg_from_bl2->h.version >= VERSION_1); 122 123 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 124 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 125 } 126 127 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 128 bl33_image_ep_info.args.arg1 = 0U; 129 bl33_image_ep_info.args.arg2 = 0U; 130 bl33_image_ep_info.args.arg3 = 0U; 131 #endif 132 133 /* 134 * Tell BL31 where the non-trusted software image 135 * is located and the entry state information 136 */ 137 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 138 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 139 140 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 141 } 142 143 static const interrupt_prop_t agx5_interrupt_props[] = { 144 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(INTR_GROUP1S), 145 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(INTR_GROUP0) 146 }; 147 148 static const gicv3_driver_data_t plat_gicv3_gic_data = { 149 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, 150 .gicr_base = PLAT_INTEL_SOCFPGA_GICR_BASE, 151 .interrupt_props = agx5_interrupt_props, 152 .interrupt_props_num = ARRAY_SIZE(agx5_interrupt_props), 153 .rdistif_num = PLATFORM_CORE_COUNT, 154 .rdistif_base_addrs = rdistif_base_addrs, 155 }; 156 157 /******************************************************************************* 158 * Perform any BL3-1 platform setup code 159 ******************************************************************************/ 160 void bl31_platform_setup(void) 161 { 162 socfpga_delay_timer_init(); 163 164 /* Initialize the gic cpu and distributor interfaces */ 165 gicv3_driver_init(&plat_gicv3_gic_data); 166 gicv3_distif_init(); 167 gicv3_rdistif_init(plat_my_core_pos()); 168 gicv3_cpuif_enable(plat_my_core_pos()); 169 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); 170 } 171 172 const mmap_region_t plat_agilex_mmap[] = { 173 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), 174 MAP_REGION_FLAT(PSS_BASE, PSS_SIZE, MT_DEVICE | MT_RW | MT_NS), 175 MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 176 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, MT_NON_CACHEABLE | MT_RW | MT_SECURE), 177 MAP_REGION_FLAT(CCU_BASE, CCU_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 178 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS), 179 MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 180 {0} 181 }; 182 183 /******************************************************************************* 184 * Perform the very early platform specific architectural setup here. At the 185 * moment this is only intializes the mmu in a quick and dirty way. 186 ******************************************************************************/ 187 void bl31_plat_arch_setup(void) 188 { 189 uint32_t boot_core = 0x00; 190 uint32_t cpuid = 0x00; 191 192 cpuid = read_mpidr(); 193 boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00); 194 NOTICE("BL31: Boot Core = %x\n", boot_core); 195 NOTICE("BL31: CPU ID = %x\n", cpuid); 196 197 } 198 199 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */ 200 uintptr_t plat_get_ns_image_entrypoint(void) 201 { 202 #ifdef PRELOADED_BL33_BASE 203 return PRELOADED_BL33_BASE; 204 #else 205 return PLAT_NS_IMAGE_OFFSET; 206 #endif 207 } 208 209 /* Get non-secure SPSR for BL33. Zephyr and Linux */ 210 uint32_t arm_get_spsr_for_bl33_entry(void) 211 { 212 unsigned int mode; 213 uint32_t spsr; 214 215 /* Figure out what mode we enter the non-secure world in */ 216 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 217 218 /* 219 * TODO: Consider the possibility of specifying the SPSR in 220 * the FIP ToC and allowing the platform to have a say as 221 * well. 222 */ 223 spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 224 return spsr; 225 } 226 227 /* SMP: Secondary cores BL31 setup reset vector */ 228 void bl31_plat_set_secondary_cpu_entrypoint(unsigned int cpu_id) 229 { 230 unsigned int pch_cpu = 0x00; 231 unsigned int pchctlr_old = 0x00; 232 unsigned int pchctlr_new = 0x00; 233 uint32_t boot_core = 0x00; 234 235 boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00); 236 /* Update the p-channel based on cpu id */ 237 pch_cpu = 1 << cpu_id; 238 239 if (boot_core == 0x00) { 240 /* Update reset vector to 0x00 */ 241 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU2, 242 (uint64_t) plat_secondary_cpus_bl31_entry >> 2); 243 } else { 244 /* Update reset vector to 0x00 */ 245 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU0, 246 (uint64_t) plat_secondary_cpus_bl31_entry >> 2); 247 } 248 249 /* Update reset vector to 0x00 */ 250 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU1, (uint64_t) plat_secondary_cpus_bl31_entry >> 2); 251 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU3, (uint64_t) plat_secondary_cpus_bl31_entry >> 2); 252 253 /* On all cores - temporary */ 254 pchctlr_old = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR)); 255 pchctlr_new = pchctlr_old | (pch_cpu<<1); 256 mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pchctlr_new); 257 258 /* We will only release the target secondary CPUs */ 259 /* Bit mask for each CPU BIT0-3 */ 260 mmio_write_32(RSTMGR_CPUSTRELEASE_CPUx, pch_cpu); 261 } 262 263 void bl31_plat_set_secondary_cpu_off(void) 264 { 265 unsigned int pch_cpu = 0x00; 266 unsigned int pch_cpu_off = 0x00; 267 unsigned int cpu_id = plat_my_core_pos(); 268 269 pch_cpu_off = 1 << cpu_id; 270 271 pch_cpu = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR)); 272 pch_cpu = pch_cpu & ~(pch_cpu_off << 1); 273 274 mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pch_cpu); 275 } 276 277 void bl31_plat_enable_mmu(uint32_t flags) 278 { 279 /* TODO: Enable mmu when needed */ 280 } 281