12f11d548SHadi Asyrafi /* 2*3905f571SJit Loon Lim * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 32f11d548SHadi Asyrafi * 42f11d548SHadi Asyrafi * SPDX-License-Identifier: BSD-3-Clause 52f11d548SHadi Asyrafi */ 62f11d548SHadi Asyrafi 72f11d548SHadi Asyrafi #ifndef AGX_PINMUX_H 82f11d548SHadi Asyrafi #define AGX_PINMUX_H 92f11d548SHadi Asyrafi 10*3905f571SJit Loon Lim #define AGX_PINMUX_BASE 0xffd13000 11*3905f571SJit Loon Lim #define AGX_PINMUX_PIN0SEL (AGX_PINMUX_BASE + 0x000) 12*3905f571SJit Loon Lim #define AGX_PINMUX_IO0CTRL (AGX_PINMUX_BASE + 0x130) 13*3905f571SJit Loon Lim #define AGX_PINMUX_EMAC0_USEFPGA (AGX_PINMUX_BASE + 0x300) 14*3905f571SJit Loon Lim #define AGX_PINMUX_EMAC1_USEFPGA (AGX_PINMUX_BASE + 0x304) 15*3905f571SJit Loon Lim #define AGX_PINMUX_EMAC2_USEFPGA (AGX_PINMUX_BASE + 0x308) 16*3905f571SJit Loon Lim #define AGX_PINMUX_NAND_USEFPGA (AGX_PINMUX_BASE + 0x320) 17*3905f571SJit Loon Lim #define AGX_PINMUX_SPIM0_USEFPGA (AGX_PINMUX_BASE + 0x328) 18*3905f571SJit Loon Lim #define AGX_PINMUX_SPIM1_USEFPGA (AGX_PINMUX_BASE + 0x32c) 19*3905f571SJit Loon Lim #define AGX_PINMUX_SDMMC_USEFPGA (AGX_PINMUX_BASE + 0x354) 20*3905f571SJit Loon Lim #define AGX_PINMUX_IO0_DELAY (AGX_PINMUX_BASE + 0x400) 21*3905f571SJit Loon Lim 22*3905f571SJit Loon Lim #define AGX_PINMUX_NAND_USEFPGA_VAL BIT(4) 23*3905f571SJit Loon Lim #define AGX_PINMUX_SDMMC_USEFPGA_VAL BIT(8) 24*3905f571SJit Loon Lim #define AGX_PINMUX_SPIM0_USEFPGA_VAL BIT(16) 25*3905f571SJit Loon Lim #define AGX_PINMUX_SPIM1_USEFPGA_VAL BIT(24) 26*3905f571SJit Loon Lim #define AGX_PINMUX_EMAC0_USEFPGA_VAL BIT(0) 27*3905f571SJit Loon Lim #define AGX_PINMUX_EMAC1_USEFPGA_VAL BIT(8) 28*3905f571SJit Loon Lim #define AGX_PINMUX_EMAC2_USEFPGA_VAL BIT(16) 292f11d548SHadi Asyrafi 30328718f2SHadi Asyrafi #include "socfpga_handoff.h" 312f11d548SHadi Asyrafi 322f11d548SHadi Asyrafi void config_pinmux(handoff *handoff); 332f11d548SHadi Asyrafi 342f11d548SHadi Asyrafi #endif 352f11d548SHadi Asyrafi 36