1 /* 2 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <assert.h> 11 #include <common/bl_common.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/ti/uart/uart_16550.h> 14 #include <lib/mmio.h> 15 #include <lib/xlat_tables/xlat_tables.h> 16 17 #include "ccu/ncore_ccu.h" 18 #include "socfpga_mailbox.h" 19 #include "socfpga_private.h" 20 #include "socfpga_sip_svc.h" 21 22 static entry_point_info_t bl32_image_ep_info; 23 static entry_point_info_t bl33_image_ep_info; 24 25 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 26 { 27 entry_point_info_t *next_image_info; 28 29 next_image_info = (type == NON_SECURE) ? 30 &bl33_image_ep_info : &bl32_image_ep_info; 31 32 /* None of the images on this platform can have 0x0 as the entrypoint */ 33 if (next_image_info->pc) 34 return next_image_info; 35 else 36 return NULL; 37 } 38 39 void setup_smmu_secure_context(void) 40 { 41 /* 42 * Program SCR0 register (0xFA000000) 43 * to set SMCFCFG bit[21] to 0x1 which raise stream match conflict fault 44 * to set CLIENTPD bit[0] to 0x0 which enables SMMU for secure context 45 */ 46 mmio_write_32(0xFA000000, 0x00200000); 47 48 /* 49 * Program SCR1 register (0xFA000004) 50 * to set NSNUMSMRGO bit[14:8] to 0x4 which stream mapping register 51 * for non-secure context and the rest will be secure context 52 * to set NSNUMCBO bit[5:0] to 0x4 which allocate context bank 53 * for non-secure context and the rest will be secure context 54 */ 55 mmio_write_32(0xFA000004, 0x00000404); 56 } 57 58 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 59 u_register_t arg2, u_register_t arg3) 60 { 61 static console_t console; 62 63 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); 64 65 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, 66 PLAT_BAUDRATE, &console); 67 /* 68 * Check params passed from BL31 should not be NULL, 69 */ 70 void *from_bl2 = (void *) arg0; 71 72 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 73 assert(params_from_bl2 != NULL); 74 75 /* 76 * Copy BL32 (if populated by BL31) and BL33 entry point information. 77 * They are stored in Secure RAM, in BL31's address space. 78 */ 79 80 if (params_from_bl2->h.type == PARAM_BL_PARAMS && 81 params_from_bl2->h.version >= VERSION_2) { 82 83 bl_params_node_t *bl_params = params_from_bl2->head; 84 85 while (bl_params) { 86 if (bl_params->image_id == BL33_IMAGE_ID) 87 bl33_image_ep_info = *bl_params->ep_info; 88 89 bl_params = bl_params->next_params_info; 90 } 91 } else { 92 struct socfpga_bl31_params *arg_from_bl2 = 93 (struct socfpga_bl31_params *) from_bl2; 94 95 assert(arg_from_bl2->h.type == PARAM_BL31); 96 assert(arg_from_bl2->h.version >= VERSION_1); 97 98 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 99 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 100 } 101 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 102 } 103 104 static const interrupt_prop_t s10_interrupt_props[] = { 105 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 106 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 107 }; 108 109 static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 110 111 static const gicv2_driver_data_t plat_gicv2_gic_data = { 112 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, 113 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, 114 .interrupt_props = s10_interrupt_props, 115 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), 116 .target_masks = target_mask_array, 117 .target_masks_num = ARRAY_SIZE(target_mask_array), 118 }; 119 120 /******************************************************************************* 121 * Perform any BL3-1 platform setup code 122 ******************************************************************************/ 123 void bl31_platform_setup(void) 124 { 125 socfpga_delay_timer_init(); 126 127 /* Initialize the gic cpu and distributor interfaces */ 128 gicv2_driver_init(&plat_gicv2_gic_data); 129 gicv2_distif_init(); 130 gicv2_pcpu_distif_init(); 131 gicv2_cpuif_enable(); 132 setup_smmu_secure_context(); 133 134 /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */ 135 mmio_write_64(PLAT_CPU_RELEASE_ADDR, 136 (uint64_t)plat_secondary_cpus_bl31_entry); 137 138 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); 139 140 ncore_enable_ocram_firewall(); 141 } 142 143 const mmap_region_t plat_agilex_mmap[] = { 144 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), 145 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS), 146 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 147 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 148 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 149 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 150 MT_DEVICE | MT_RW | MT_SECURE), 151 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS), 152 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS), 153 {0} 154 }; 155 156 /******************************************************************************* 157 * Perform the very early platform specific architectural setup here. At the 158 * moment this is only initializes the mmu in a quick and dirty way. 159 ******************************************************************************/ 160 void bl31_plat_arch_setup(void) 161 { 162 const mmap_region_t bl_regions[] = { 163 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 164 MT_MEMORY | MT_RW | MT_SECURE), 165 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 166 MT_CODE | MT_SECURE), 167 MAP_REGION_FLAT(BL_RO_DATA_BASE, 168 BL_RO_DATA_END - BL_RO_DATA_BASE, 169 MT_RO_DATA | MT_SECURE), 170 #if USE_COHERENT_MEM 171 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 172 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 173 MT_DEVICE | MT_RW | MT_SECURE), 174 #endif 175 {0} 176 }; 177 178 setup_page_tables(bl_regions, plat_agilex_mmap); 179 enable_mmu_el3(0); 180 } 181 182