1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <assert.h> 11 #include <common/bl_common.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/ti/uart/uart_16550.h> 14 #include <lib/xlat_tables/xlat_tables.h> 15 #include <platform_def.h> 16 17 18 static entry_point_info_t bl32_image_ep_info; 19 static entry_point_info_t bl33_image_ep_info; 20 21 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 22 { 23 entry_point_info_t *next_image_info; 24 25 next_image_info = (type == NON_SECURE) ? 26 &bl33_image_ep_info : &bl32_image_ep_info; 27 28 /* None of the images on this platform can have 0x0 as the entrypoint */ 29 if (next_image_info->pc) 30 return next_image_info; 31 else 32 return NULL; 33 } 34 35 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 36 u_register_t arg2, u_register_t arg3) 37 { 38 static console_16550_t console; 39 40 console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, 41 &console); 42 /* 43 * Check params passed from BL31 should not be NULL, 44 */ 45 void *from_bl2 = (void *) arg0; 46 47 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 48 49 assert(params_from_bl2 != NULL); 50 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 51 assert(params_from_bl2->h.version >= VERSION_2); 52 53 /* 54 * Copy BL32 (if populated by BL31) and BL33 entry point information. 55 * They are stored in Secure RAM, in BL31's address space. 56 */ 57 58 bl_params_node_t *bl_params = params_from_bl2->head; 59 60 while (bl_params) { 61 if (bl_params->image_id == BL33_IMAGE_ID) 62 bl33_image_ep_info = *bl_params->ep_info; 63 64 bl_params = bl_params->next_params_info; 65 } 66 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 67 } 68 69 static const interrupt_prop_t s10_interrupt_props[] = { 70 PLAT_INTEL_AGX_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 71 PLAT_INTEL_AGX_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 72 }; 73 74 static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 75 76 static const gicv2_driver_data_t plat_gicv2_gic_data = { 77 .gicd_base = PLAT_INTEL_AGX_GICD_BASE, 78 .gicc_base = PLAT_INTEL_AGX_GICC_BASE, 79 .interrupt_props = s10_interrupt_props, 80 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), 81 .target_masks = target_mask_array, 82 .target_masks_num = ARRAY_SIZE(target_mask_array), 83 }; 84 85 /******************************************************************************* 86 * Perform any BL3-1 platform setup code 87 ******************************************************************************/ 88 void bl31_platform_setup(void) 89 { 90 /* Initialize the gic cpu and distributor interfaces */ 91 gicv2_driver_init(&plat_gicv2_gic_data); 92 gicv2_distif_init(); 93 gicv2_pcpu_distif_init(); 94 gicv2_cpuif_enable(); 95 } 96 97 const mmap_region_t plat_agilex_mmap[] = { 98 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), 99 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS), 100 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 101 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 102 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 103 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 104 MT_DEVICE | MT_RW | MT_SECURE), 105 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS), 106 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS), 107 {0}, 108 }; 109 110 /******************************************************************************* 111 * Perform the very early platform specific architectural setup here. At the 112 * moment this is only intializes the mmu in a quick and dirty way. 113 ******************************************************************************/ 114 void bl31_plat_arch_setup(void) 115 { 116 const mmap_region_t bl_regions[] = { 117 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 118 MT_MEMORY | MT_RW | MT_SECURE), 119 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 120 MT_CODE | MT_SECURE), 121 MAP_REGION_FLAT(BL_RO_DATA_BASE, 122 BL_RO_DATA_END - BL_RO_DATA_BASE, 123 MT_RO_DATA | MT_SECURE), 124 #if USE_COHERENT_MEM 125 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 126 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 127 MT_DEVICE | MT_RW | MT_SECURE), 128 #endif 129 {0}, 130 }; 131 132 setup_page_tables(bl_regions, plat_agilex_mmap); 133 enable_mmu_el3(0); 134 } 135 136