1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <assert.h> 11 #include <common/bl_common.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/ti/uart/uart_16550.h> 14 #include <lib/mmio.h> 15 #include <lib/xlat_tables/xlat_tables.h> 16 17 #include "socfpga_private.h" 18 19 static entry_point_info_t bl32_image_ep_info; 20 static entry_point_info_t bl33_image_ep_info; 21 22 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 23 { 24 entry_point_info_t *next_image_info; 25 26 next_image_info = (type == NON_SECURE) ? 27 &bl33_image_ep_info : &bl32_image_ep_info; 28 29 /* None of the images on this platform can have 0x0 as the entrypoint */ 30 if (next_image_info->pc) 31 return next_image_info; 32 else 33 return NULL; 34 } 35 36 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 37 u_register_t arg2, u_register_t arg3) 38 { 39 static console_16550_t console; 40 41 console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, 42 &console); 43 /* 44 * Check params passed from BL31 should not be NULL, 45 */ 46 void *from_bl2 = (void *) arg0; 47 48 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 49 assert(params_from_bl2 != NULL); 50 51 /* 52 * Copy BL32 (if populated by BL31) and BL33 entry point information. 53 * They are stored in Secure RAM, in BL31's address space. 54 */ 55 56 if (params_from_bl2->h.type == PARAM_BL_PARAMS && 57 params_from_bl2->h.version >= VERSION_2) { 58 59 bl_params_node_t *bl_params = params_from_bl2->head; 60 61 while (bl_params) { 62 if (bl_params->image_id == BL33_IMAGE_ID) 63 bl33_image_ep_info = *bl_params->ep_info; 64 65 bl_params = bl_params->next_params_info; 66 } 67 } else { 68 struct socfpga_bl31_params *arg_from_bl2 = 69 (struct socfpga_bl31_params *) from_bl2; 70 71 assert(arg_from_bl2->h.type == PARAM_BL31); 72 assert(arg_from_bl2->h.version >= VERSION_1); 73 74 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 75 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 76 } 77 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 78 } 79 80 static const interrupt_prop_t s10_interrupt_props[] = { 81 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 82 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 83 }; 84 85 static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 86 87 static const gicv2_driver_data_t plat_gicv2_gic_data = { 88 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, 89 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, 90 .interrupt_props = s10_interrupt_props, 91 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), 92 .target_masks = target_mask_array, 93 .target_masks_num = ARRAY_SIZE(target_mask_array), 94 }; 95 96 /******************************************************************************* 97 * Perform any BL3-1 platform setup code 98 ******************************************************************************/ 99 void bl31_platform_setup(void) 100 { 101 /* Initialize the gic cpu and distributor interfaces */ 102 gicv2_driver_init(&plat_gicv2_gic_data); 103 gicv2_distif_init(); 104 gicv2_pcpu_distif_init(); 105 gicv2_cpuif_enable(); 106 107 /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */ 108 mmio_write_64(PLAT_CPU_RELEASE_ADDR, 109 (uint64_t)plat_secondary_cpus_bl31_entry); 110 } 111 112 const mmap_region_t plat_agilex_mmap[] = { 113 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), 114 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS), 115 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 116 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 117 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 118 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 119 MT_DEVICE | MT_RW | MT_SECURE), 120 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS), 121 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS), 122 {0} 123 }; 124 125 /******************************************************************************* 126 * Perform the very early platform specific architectural setup here. At the 127 * moment this is only intializes the mmu in a quick and dirty way. 128 ******************************************************************************/ 129 void bl31_plat_arch_setup(void) 130 { 131 const mmap_region_t bl_regions[] = { 132 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 133 MT_MEMORY | MT_RW | MT_SECURE), 134 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 135 MT_CODE | MT_SECURE), 136 MAP_REGION_FLAT(BL_RO_DATA_BASE, 137 BL_RO_DATA_END - BL_RO_DATA_BASE, 138 MT_RO_DATA | MT_SECURE), 139 #if USE_COHERENT_MEM 140 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 141 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 142 MT_DEVICE | MT_RW | MT_SECURE), 143 #endif 144 {0} 145 }; 146 147 setup_page_tables(bl_regions, plat_agilex_mmap); 148 enable_mmu_el3(0); 149 } 150 151