1 /* 2 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <assert.h> 12 #include <common/bl_common.h> 13 #include <drivers/arm/gicv2.h> 14 #include <drivers/ti/uart/uart_16550.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables.h> 17 #include <plat/common/platform.h> 18 19 #include "ccu/ncore_ccu.h" 20 #include "socfpga_mailbox.h" 21 #include "socfpga_private.h" 22 #include "socfpga_sip_svc.h" 23 24 /* Get non-secure SPSR for BL33. Zephyr and Linux */ 25 uint32_t arm_get_spsr_for_bl33_entry(void); 26 27 static entry_point_info_t bl32_image_ep_info; 28 static entry_point_info_t bl33_image_ep_info; 29 30 /* Clear SMMU Cache Unlock */ 31 static void configure_smmu_cache_unlock(uintptr_t smmu_base); 32 33 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 34 { 35 entry_point_info_t *next_image_info; 36 37 next_image_info = (type == NON_SECURE) ? 38 &bl33_image_ep_info : &bl32_image_ep_info; 39 40 /* None of the images on this platform can have 0x0 as the entrypoint */ 41 if (next_image_info->pc) 42 return next_image_info; 43 else 44 return NULL; 45 } 46 47 void setup_smmu_secure_context(void) 48 { 49 /* 50 * Program SCR0 register (0xFA000000) 51 * to set SMCFCFG bit[21] to 0x1 which raise stream match conflict fault 52 * to set CLIENTPD bit[0] to 0x0 which enables SMMU for secure context 53 */ 54 mmio_write_32(0xFA000000, 0x00200000); 55 56 /* 57 * Program SCR1 register (0xFA000004) 58 * to set NSNUMSMRGO bit[14:8] to 0x4 which stream mapping register 59 * for non-secure context and the rest will be secure context 60 * to set NSNUMCBO bit[5:0] to 0x4 which allocate context bank 61 * for non-secure context and the rest will be secure context 62 */ 63 mmio_write_32(0xFA000004, 0x00000404); 64 } 65 66 67 static void configure_smmu_cache_unlock(uintptr_t smmu_base) 68 { 69 uint32_t version = 0; 70 71 version = mmio_read_32(smmu_base + SMMU_IDR7); 72 VERBOSE("SOCFPGA: SMMU(0x%lx) r%dp%d\n", smmu_base, 73 SMMU_IDR7_MAJOR(version), SMMU_IDR7_MINOR(version)); 74 75 /* For SMMU r2p0+ clear CACHE_LOCK to allow writes to CBn_ACTLR */ 76 if (SMMU_IDR7_MAJOR(version) >= 2) { 77 mmio_clrbits_32(smmu_base + SMMU_SACR, SMMU_SACR_CACHE_LOCK); 78 } 79 } 80 81 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 82 u_register_t arg2, u_register_t arg3) 83 { 84 static console_t console; 85 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); 86 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, 87 PLAT_BAUDRATE, &console); 88 89 /* Enable TF-A BL31 logs when running from non-secure world also. */ 90 console_set_scope(&console, 91 (CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH)); 92 93 /* 94 * Check params passed from BL31 should not be NULL, 95 */ 96 void *from_bl2 = (void *) arg0; 97 98 #if RESET_TO_BL31 99 /* There are no parameters from BL2 if BL31 is a reset vector */ 100 assert(from_bl2 == NULL); 101 void *plat_params_from_bl2 = (void *) arg3; 102 103 assert(plat_params_from_bl2 == NULL); 104 105 /* Populate entry point information for BL33 */ 106 SET_PARAM_HEAD(&bl33_image_ep_info, 107 PARAM_EP, 108 VERSION_1, 109 0); 110 111 # if ARM_LINUX_KERNEL_AS_BL33 112 /* 113 * According to the file ``Documentation/arm64/booting.txt`` of the 114 * Linux kernel tree, Linux expects the physical address of the device 115 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 116 * must be 0. 117 */ 118 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 119 bl33_image_ep_info.args.arg1 = 0U; 120 bl33_image_ep_info.args.arg2 = 0U; 121 bl33_image_ep_info.args.arg3 = 0U; 122 # endif 123 124 #else /* RESET_TO_BL31 */ 125 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 126 assert(params_from_bl2 != NULL); 127 128 /* 129 * Copy BL32 (if populated by BL31) and BL33 entry point information. 130 * They are stored in Secure RAM, in BL31's address space. 131 */ 132 if (params_from_bl2->h.type == PARAM_BL_PARAMS && 133 params_from_bl2->h.version >= VERSION_2) { 134 bl_params_node_t *bl_params = params_from_bl2->head; 135 while (bl_params) { 136 if (bl_params->image_id == BL33_IMAGE_ID) 137 bl33_image_ep_info = *bl_params->ep_info; 138 bl_params = bl_params->next_params_info; 139 } 140 } else { 141 struct socfpga_bl31_params *arg_from_bl2 = 142 (struct socfpga_bl31_params *) from_bl2; 143 assert(arg_from_bl2->h.type == PARAM_BL31); 144 assert(arg_from_bl2->h.version >= VERSION_1); 145 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 146 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 147 } 148 149 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 150 bl33_image_ep_info.args.arg1 = 0U; 151 bl33_image_ep_info.args.arg2 = 0U; 152 bl33_image_ep_info.args.arg3 = 0U; 153 #endif 154 155 /* 156 * Tell BL31 where the non-trusted software image 157 * is located and the entry state information 158 */ 159 # if ARM_LINUX_KERNEL_AS_BL33 160 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 161 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 162 #endif 163 164 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 165 } 166 167 static const interrupt_prop_t s10_interrupt_props[] = { 168 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 169 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 170 }; 171 172 static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 173 174 static const gicv2_driver_data_t plat_gicv2_gic_data = { 175 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, 176 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, 177 .interrupt_props = s10_interrupt_props, 178 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), 179 .target_masks = target_mask_array, 180 .target_masks_num = ARRAY_SIZE(target_mask_array), 181 }; 182 183 /******************************************************************************* 184 * Perform any BL3-1 platform setup code 185 ******************************************************************************/ 186 void bl31_platform_setup(void) 187 { 188 socfpga_delay_timer_init(); 189 190 /* Initialize the gic cpu and distributor interfaces */ 191 gicv2_driver_init(&plat_gicv2_gic_data); 192 gicv2_distif_init(); 193 gicv2_pcpu_distif_init(); 194 gicv2_cpuif_enable(); 195 setup_smmu_secure_context(); 196 configure_smmu_cache_unlock(SMMU_REG_BASE); 197 198 /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */ 199 mmio_write_64(PLAT_CPU_RELEASE_ADDR, 200 (uint64_t)plat_secondary_cpus_bl31_entry); 201 202 #if SIP_SVC_V3 203 /* 204 * Re-initialize the mailbox to include V3 specific routines. 205 * In V3, this re-initialize is required because prior to BL31, U-Boot 206 * SPL has its own mailbox settings and this initialization will 207 * override to those settings as required by the V3 framework. 208 */ 209 mailbox_init(); 210 #endif 211 212 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); 213 } 214 215 const mmap_region_t plat_agilex_mmap[] = { 216 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), 217 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS), 218 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 219 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 220 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 221 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 222 MT_DEVICE | MT_RW | MT_SECURE), 223 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS), 224 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS), 225 {0} 226 }; 227 228 /******************************************************************************* 229 * Perform the very early platform specific architectural setup here. At the 230 * moment this is only initializes the mmu in a quick and dirty way. 231 ******************************************************************************/ 232 void bl31_plat_arch_setup(void) 233 { 234 const mmap_region_t bl_regions[] = { 235 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 236 MT_MEMORY | MT_RW | MT_SECURE), 237 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 238 MT_CODE | MT_SECURE), 239 MAP_REGION_FLAT(BL_RO_DATA_BASE, 240 BL_RO_DATA_END - BL_RO_DATA_BASE, 241 MT_RO_DATA | MT_SECURE), 242 #if USE_COHERENT_MEM 243 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 244 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 245 MT_DEVICE | MT_RW | MT_SECURE), 246 #endif 247 {0} 248 }; 249 setup_page_tables(bl_regions, plat_agilex_mmap); 250 enable_mmu_el3(0); 251 } 252 253 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */ 254 uintptr_t plat_get_ns_image_entrypoint(void) 255 { 256 #ifdef PRELOADED_BL33_BASE 257 return PRELOADED_BL33_BASE; 258 #else 259 return PLAT_NS_IMAGE_OFFSET; 260 #endif 261 } 262 263 /* Get non-secure SPSR for BL33. Zephyr and Linux */ 264 uint32_t arm_get_spsr_for_bl33_entry(void) 265 { 266 unsigned int mode; 267 uint32_t spsr; 268 269 /* Figure out what mode we enter the non-secure world in */ 270 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 271 272 /* 273 * TODO: Consider the possibility of specifying the SPSR in 274 * the FIP ToC and allowing the platform to have a say as 275 * well. 276 */ 277 spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 278 return spsr; 279 } 280