1 /* 2 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2020, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <common/bl_common.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/generic_delay_timer.h> 14 #include <drivers/synopsys/dw_mmc.h> 15 #include <drivers/ti/uart/uart_16550.h> 16 #include <lib/xlat_tables/xlat_tables.h> 17 18 #include "agilex_mmc.h" 19 #include "agilex_clock_manager.h" 20 #include "agilex_memory_controller.h" 21 #include "agilex_pinmux.h" 22 #include "ccu/ncore_ccu.h" 23 #include "qspi/cadence_qspi.h" 24 #include "socfpga_emac.h" 25 #include "socfpga_handoff.h" 26 #include "socfpga_mailbox.h" 27 #include "socfpga_private.h" 28 #include "socfpga_reset_manager.h" 29 #include "socfpga_system_manager.h" 30 #include "wdt/watchdog.h" 31 32 33 const mmap_region_t agilex_plat_mmap[] = { 34 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 35 MT_MEMORY | MT_RW | MT_NS), 36 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 37 MT_DEVICE | MT_RW | MT_NS), 38 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 39 MT_DEVICE | MT_RW | MT_SECURE), 40 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 41 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 42 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 43 MT_DEVICE | MT_RW | MT_SECURE), 44 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 45 MT_DEVICE | MT_RW | MT_NS), 46 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 47 MT_DEVICE | MT_RW | MT_NS), 48 {0}, 49 }; 50 51 boot_source_type boot_source = BOOT_SOURCE; 52 53 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 54 u_register_t x2, u_register_t x4) 55 { 56 static console_t console; 57 handoff reverse_handoff_ptr; 58 59 generic_delay_timer_init(); 60 61 if (socfpga_get_handoff(&reverse_handoff_ptr)) 62 return; 63 config_pinmux(&reverse_handoff_ptr); 64 config_clkmgr_handoff(&reverse_handoff_ptr); 65 66 enable_nonsecure_access(); 67 deassert_peripheral_reset(); 68 config_hps_hs_before_warm_reset(); 69 70 watchdog_init(get_wdt_clk()); 71 72 console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE, 73 &console); 74 75 socfpga_delay_timer_init(); 76 init_ncore_ccu(); 77 socfpga_emac_init(); 78 init_hard_memory_controller(); 79 mailbox_init(); 80 agx_mmc_init(); 81 82 if (!intel_mailbox_is_fpga_not_ready()) 83 socfpga_bridges_enable(); 84 } 85 86 87 void bl2_el3_plat_arch_setup(void) 88 { 89 90 struct mmc_device_info info; 91 const mmap_region_t bl_regions[] = { 92 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, 93 MT_MEMORY | MT_RW | MT_SECURE), 94 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 95 MT_CODE | MT_SECURE), 96 MAP_REGION_FLAT(BL_RO_DATA_BASE, 97 BL_RO_DATA_END - BL_RO_DATA_BASE, 98 MT_RO_DATA | MT_SECURE), 99 #if USE_COHERENT_MEM_BAR 100 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 101 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 102 MT_DEVICE | MT_RW | MT_SECURE), 103 #endif 104 {0}, 105 }; 106 107 setup_page_tables(bl_regions, agilex_plat_mmap); 108 109 enable_mmu_el3(0); 110 111 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); 112 113 info.mmc_dev_type = MMC_IS_SD; 114 info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 115 116 switch (boot_source) { 117 case BOOT_SOURCE_SDMMC: 118 dw_mmc_init(¶ms, &info); 119 socfpga_io_setup(boot_source); 120 break; 121 122 case BOOT_SOURCE_QSPI: 123 mailbox_set_qspi_open(); 124 mailbox_set_qspi_direct(); 125 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 126 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 127 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 128 socfpga_io_setup(boot_source); 129 break; 130 131 default: 132 ERROR("Unsupported boot source\n"); 133 panic(); 134 break; 135 } 136 } 137 138 uint32_t get_spsr_for_bl33_entry(void) 139 { 140 unsigned long el_status; 141 unsigned int mode; 142 uint32_t spsr; 143 144 /* Figure out what mode we enter the non-secure world in */ 145 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 146 el_status &= ID_AA64PFR0_ELX_MASK; 147 148 mode = (el_status) ? MODE_EL2 : MODE_EL1; 149 150 /* 151 * TODO: Consider the possibility of specifying the SPSR in 152 * the FIP ToC and allowing the platform to have a say as 153 * well. 154 */ 155 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 156 return spsr; 157 } 158 159 160 int bl2_plat_handle_post_image_load(unsigned int image_id) 161 { 162 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 163 164 switch (image_id) { 165 case BL33_IMAGE_ID: 166 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 167 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 168 break; 169 default: 170 break; 171 } 172 173 return 0; 174 } 175 176 /******************************************************************************* 177 * Perform any BL3-1 platform setup code 178 ******************************************************************************/ 179 void bl2_platform_setup(void) 180 { 181 } 182 183