1*4ddfb6f1SJacky Bai /* 2*4ddfb6f1SJacky Bai * Copyright 2022-2025 NXP 3*4ddfb6f1SJacky Bai * 4*4ddfb6f1SJacky Bai * SPDX-License-Identifier: BSD-3-Clause 5*4ddfb6f1SJacky Bai */ 6*4ddfb6f1SJacky Bai 7*4ddfb6f1SJacky Bai #include <arch.h> 8*4ddfb6f1SJacky Bai #include <arch_helpers.h> 9*4ddfb6f1SJacky Bai #include <plat/common/platform.h> 10*4ddfb6f1SJacky Bai 11*4ddfb6f1SJacky Bai const unsigned char imx_power_domain_tree_desc[] = { 12*4ddfb6f1SJacky Bai PWR_DOMAIN_AT_MAX_LVL, 13*4ddfb6f1SJacky Bai PLATFORM_CLUSTER_COUNT, 14*4ddfb6f1SJacky Bai PLATFORM_CLUSTER0_CORE_COUNT, 15*4ddfb6f1SJacky Bai }; 16*4ddfb6f1SJacky Bai plat_get_power_domain_tree_desc(void)17*4ddfb6f1SJacky Baiconst unsigned char *plat_get_power_domain_tree_desc(void) 18*4ddfb6f1SJacky Bai { 19*4ddfb6f1SJacky Bai return imx_power_domain_tree_desc; 20*4ddfb6f1SJacky Bai } 21*4ddfb6f1SJacky Bai 22*4ddfb6f1SJacky Bai /* 23*4ddfb6f1SJacky Bai * Only one cluster is planned for i.MX9 family, no need 24*4ddfb6f1SJacky Bai * to consider the cluster id 25*4ddfb6f1SJacky Bai */ plat_core_pos_by_mpidr(u_register_t mpidr)26*4ddfb6f1SJacky Baiint plat_core_pos_by_mpidr(u_register_t mpidr) 27*4ddfb6f1SJacky Bai { 28*4ddfb6f1SJacky Bai unsigned int cpu_id; 29*4ddfb6f1SJacky Bai 30*4ddfb6f1SJacky Bai mpidr &= MPIDR_AFFINITY_MASK; 31*4ddfb6f1SJacky Bai 32*4ddfb6f1SJacky Bai if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { 33*4ddfb6f1SJacky Bai return -1; 34*4ddfb6f1SJacky Bai } 35*4ddfb6f1SJacky Bai 36*4ddfb6f1SJacky Bai cpu_id = MPIDR_AFFLVL1_VAL(mpidr); 37*4ddfb6f1SJacky Bai 38*4ddfb6f1SJacky Bai return cpu_id; 39*4ddfb6f1SJacky Bai } 40