1 /* 2 * Copyright 2020-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <xrdc.h> 8 9 #define SP(X) ((X) << 9) 10 #define SU(X) ((X) << 6) 11 #define NP(X) ((X) << 3) 12 #define NU(X) ((X) << 0) 13 14 #define RWX 7 15 #define RW 6 16 #define R 4 17 #define X 1 18 19 struct xrdc_mda_config imx8ulp_mda[] = { 20 { 0, 7, MDA_SA_PT }, /* A core */ 21 { 1, 1, MDA_SA_NS }, /* DMA1 */ 22 { 2, 1, MDA_SA_NS }, /* USB */ 23 { 3, 1, MDA_SA_NS }, /* PXP-> .M10 */ 24 { 4, 1, MDA_SA_NS }, /* ENET */ 25 { 5, 1, MDA_SA_PT }, /* CAAM */ 26 { 6, 1, MDA_SA_NS }, /* USDHC0 */ 27 { 7, 1, MDA_SA_NS }, /* USDHC1 */ 28 { 8, 1, MDA_SA_NS }, /* USDHC2 */ 29 { 9, 2, MDA_SA_NS }, /* HIFI4 */ 30 { 10, 3, MDA_SA_NS }, /* GPU3D */ 31 { 11, 3, MDA_SA_NS }, /* GPU2D */ 32 { 12, 3, MDA_SA_NS }, /* EPDC */ 33 { 13, 3, MDA_SA_NS }, /* DCNano */ 34 { 14, 3, MDA_SA_NS }, /* ISI */ 35 { 15, 3, MDA_SA_NS }, /* PXP->NIC_LPAV.M0 */ 36 { 16, 3, MDA_SA_NS }, /* DMA2 */ 37 }; 38 39 struct xrdc_mrc_config imx8ulp_mrc[] = { 40 { 0, 0, 0x0, 0x30000, {0, 0, 0, 0, 0, 0, 0, 1}, {0xfff, 0} }, /* ROM1 */ 41 { 1, 0, 0x60000000, 0x10000000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* Flexspi2 */ 42 { 2, 0, 0x22020000, 0x40000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM2 */ 43 { 3, 0, 0x22010000, 0x10000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM0 */ 44 { 4, 0, 0x80000000, 0x80000000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* DRAM */ 45 { 5, 0, 0x80000000, 0x80000000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* DRAM */ 46 { 6, 0, 0x80000000, 0x80000000, {1, 1, 0, 1, 1, 0, 1, 0}, {0xfff, 0} }, /* DRAM for LPAV and RTD*/ 47 { 7, 0, 0x80000000, 0x10000000, {0, 0, 1, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for HIFI4 */ 48 { 7, 1, 0x90000000, 0x10000000, {0, 0, 1, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for HIFI4 */ 49 { 8, 0, 0x21000000, 0x10000, {1, 1, 1, 1, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM1 */ 50 { 9, 0, 0x1ffc0000, 0xc0000, {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0} }, /* SSRAM for HIFI4 */ 51 { 10, 0, 0x1ffc0000, 0xc0000, {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0} }, /* SSRAM for LPAV */ 52 { 11, 0, 0x21170000, 0x10000, {0, 0, 1, 0, 0, 0, 0, 2}, {0xfff, SP(RW) | SU(RW) | NP(RW)} }, /* HIFI4 TCM */ 53 { 11, 1, 0x21180000, 0x10000, {0, 0, 1, 0, 0, 0, 0, 2}, {SP(RW) | SU(RW) | NP(RW) | NU(RW), SP(RW) | SU(RW) | NP(RW)} }, /* HIFI4 TCM */ 54 { 12, 0, 0x2d400000, 0x100000, {0, 0, 0, 0, 0, 0, 0, 1}, {SP(RW) | SU(RW) | NP(RW) | NU(RW), 0} }, /* GIC500 */ 55 }; 56 57 struct xrdc_pac_msc_config imx8ulp_pdac[] = { 58 { 0, PAC_SLOT_ALL, {0, 7, 0, 0, 0, 0, 0, 7} }, /* PAC0 */ 59 { 0, 36, {0, 0, 0, 0, 0, 0, 7, 7} }, /* PAC0 slot 36 for CMC1 */ 60 { 0, 41, {0, 0, 0, 0, 0, 0, 7, 7} }, /* PAC0 slot 41 for SIM_AD */ 61 { 1, PAC_SLOT_ALL, {0, 7, 0, 0, 0, 0, 0, 7} }, /* PAC1 */ 62 { 1, 0, {0, 7, 0, 0, 0, 0, 7, 7} }, /* PAC1 slot 0 for PCC4 */ 63 { 1, 6, {0, 7, 7, 0, 0, 0, 0, 7} }, /* PAC1 slot 6 for LPUART6 */ 64 { 1, 9, {0, 7, 7, 7, 0, 0, 0, 7} }, /* SAI5 for HIFI4 and eDMA2 */ 65 { 1, 12, {0, 7, 0, 0, 0, 0, 7, 7} }, /* PAC1 slot 12 for IOMUXC1 */ 66 { 2, PAC_SLOT_ALL, {7, 7, 7, 7, 0, 0, 7, 7} }, /* PAC2 */ 67 }; 68 69 struct xrdc_pac_msc_config imx8ulp_msc[] = { 70 { 0, 0, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC0 GPIOE */ 71 { 0, 1, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC0 GPIOF */ 72 { 1, MSC_SLOT_ALL, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC1 GPIOD */ 73 { 2, MSC_SLOT_ALL, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC2 GPU3D/2D/DCNANO/DDR registers */ 74 }; 75