1*7c5eedcaSPankaj Gupta /* 2*7c5eedcaSPankaj Gupta * Copyright 2021-2024 NXP. 3*7c5eedcaSPankaj Gupta * 4*7c5eedcaSPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*7c5eedcaSPankaj Gupta */ 6*7c5eedcaSPankaj Gupta 7*7c5eedcaSPankaj Gupta #include <lib/mmio.h> 8*7c5eedcaSPankaj Gupta 9*7c5eedcaSPankaj Gupta #include <imx8ulp_caam.h> 10*7c5eedcaSPankaj Gupta 11*7c5eedcaSPankaj Gupta void imx8ulp_caam_init(void) 12*7c5eedcaSPankaj Gupta { 13*7c5eedcaSPankaj Gupta /* config CAAM JRaMID set MID to Cortex A */ 14*7c5eedcaSPankaj Gupta mmio_write_32(CAAM_JR0MID, CAAM_NS_MID); 15*7c5eedcaSPankaj Gupta mmio_write_32(CAAM_JR1MID, CAAM_NS_MID); 16*7c5eedcaSPankaj Gupta mmio_write_32(CAAM_JR2MID, CAAM_NS_MID); 17*7c5eedcaSPankaj Gupta mmio_write_32(CAAM_JR3MID, CAAM_NS_MID); 18*7c5eedcaSPankaj Gupta } 19