1 /* 2 * Copyright 2021-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/console.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <lib/el3_runtime/context_mgmt.h> 17 #include <lib/mmio.h> 18 #include <lib/xlat_tables/xlat_tables_v2.h> 19 #include <plat/common/platform.h> 20 #include <platform_def.h> 21 22 #include <dram.h> 23 #include <imx8_lpuart.h> 24 #include <imx8ulp_caam.h> 25 #include <imx_plat_common.h> 26 #include <plat_imx8.h> 27 #include <upower_api.h> 28 #include <xrdc.h> 29 30 #define MAP_BL31_TOTAL \ 31 MAP_REGION_FLAT(BL31_BASE, BL31_LIMIT - BL31_BASE, MT_MEMORY | MT_RW | MT_SECURE) 32 #define MAP_BL31_RO \ 33 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 34 #define MAP_BL32_TOTAL MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 35 #define MAP_COHERENT_MEM \ 36 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), \ 37 MT_DEVICE | MT_RW | MT_SECURE) 38 39 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 40 41 static const mmap_region_t imx_mmap[] = { 42 DEVICE0_MAP, DEVICE1_MAP, DEVICE2_MAP, 43 ELE_MAP, SEC_SIM_MAP, SRAM0_MAP, 44 {0} 45 }; 46 47 extern uint32_t upower_init(void); 48 extern void imx8ulp_init_scmi_server(void); 49 50 static entry_point_info_t bl32_image_ep_info; 51 static entry_point_info_t bl33_image_ep_info; 52 53 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 54 u_register_t arg2, u_register_t arg3) 55 { 56 static console_t console; 57 58 /* config the TPM5 clock */ 59 mmio_write_32(IMX_PCC3_BASE + 0xd0, 0x92000000); 60 mmio_write_32(IMX_PCC3_BASE + 0xd0, 0xd2000000); 61 62 /* enable the GPIO D,E,F non-secure access by default */ 63 mmio_write_32(IMX_PCC4_BASE + 0x78, 0xc0000000); 64 mmio_write_32(IMX_PCC4_BASE + 0x7c, 0xc0000000); 65 mmio_write_32(IMX_PCC5_BASE + 0x114, 0xc0000000); 66 67 mmio_write_32(IMX_GPIOE_BASE + 0x10, 0xffffffff); 68 mmio_write_32(IMX_GPIOE_BASE + 0x14, 0x3); 69 mmio_write_32(IMX_GPIOE_BASE + 0x18, 0xffffffff); 70 mmio_write_32(IMX_GPIOE_BASE + 0x1c, 0x3); 71 72 mmio_write_32(IMX_GPIOF_BASE + 0x10, 0xffffffff); 73 mmio_write_32(IMX_GPIOF_BASE + 0x14, 0x3); 74 mmio_write_32(IMX_GPIOF_BASE + 0x18, 0xffffffff); 75 mmio_write_32(IMX_GPIOF_BASE + 0x1c, 0x3); 76 77 mmio_write_32(IMX_GPIOD_BASE + 0x10, 0xffffffff); 78 mmio_write_32(IMX_GPIOD_BASE + 0x14, 0x3); 79 mmio_write_32(IMX_GPIOD_BASE + 0x18, 0xffffffff); 80 mmio_write_32(IMX_GPIOD_BASE + 0x1c, 0x3); 81 82 console_lpuart_register(IMX_LPUART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 83 IMX_CONSOLE_BAUDRATE, &console); 84 85 /* This console is only used for boot stage */ 86 console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); 87 88 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 89 bl33_image_ep_info.spsr = plat_get_spsr_for_bl33_entry(); 90 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 91 92 #if defined(SPD_opteed) || defined(SPD_trusty) 93 /* Populate entry point information for BL32 */ 94 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 95 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 96 bl32_image_ep_info.pc = BL32_BASE; 97 bl32_image_ep_info.spsr = 0; 98 99 /* Pass TEE base and size to bl33 */ 100 bl33_image_ep_info.args.arg1 = BL32_BASE; 101 bl33_image_ep_info.args.arg2 = BL32_SIZE; 102 103 #ifdef SPD_trusty 104 bl32_image_ep_info.args.arg0 = BL32_SIZE; 105 bl32_image_ep_info.args.arg1 = BL32_BASE; 106 #else 107 /* Make sure memory is clean */ 108 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 109 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 110 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 111 #endif 112 #endif 113 } 114 115 void bl31_plat_arch_setup(void) 116 { 117 const mmap_region_t bl_regions[] = { 118 MAP_BL31_TOTAL, 119 MAP_BL31_RO, 120 #if USE_COHERENT_MEM 121 MAP_COHERENT_MEM, 122 #endif 123 #if defined(SPD_opteed) || defined(SPD_trusty) 124 MAP_BL32_TOTAL, 125 #endif 126 {0}, 127 }; 128 129 setup_page_tables(bl_regions, imx_mmap); 130 enable_mmu_el3(0); 131 132 /* TODO: Hack, refine this piece, scmi channel free */ 133 mmio_write_32(SRAM0_BASE + 0x4, 1); 134 135 /* Allow M core to reset A core */ 136 mmio_clrbits_32(IMX_MU0B_BASE + 0x10, BIT(2)); 137 } 138 139 void bl31_platform_setup(void) 140 { 141 /* select the arch timer source */ 142 mmio_setbits_32(IMX_SIM1_BASE + 0x30, 0x8000000); 143 144 generic_delay_timer_init(); 145 146 plat_gic_driver_init(); 147 plat_gic_init(); 148 149 imx8ulp_init_scmi_server(); 150 upower_init(); 151 152 xrdc_apply_apd_config(); 153 xrdc_apply_lpav_config(); 154 xrdc_enable(); 155 156 imx8ulp_caam_init(); 157 158 dram_init(); 159 } 160 161 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 162 { 163 if (type == NON_SECURE) { 164 return &bl33_image_ep_info; 165 } else { 166 return &bl32_image_ep_info; 167 } 168 } 169 170 unsigned int plat_get_syscnt_freq2(void) 171 { 172 return COUNTER_FREQUENCY; 173 } 174 175 void bl31_plat_runtime_setup(void) 176 { 177 } 178 179 #ifdef SPD_trusty 180 void plat_trusty_set_boot_args(aapcs64_params_t *args) 181 { 182 args->arg0 = BL32_SIZE; 183 args->arg1 = BL32_BASE; 184 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 185 } 186 #endif 187