1 /* 2 * Copyright 2021-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <drivers/delay_timer.h> 11 #include <lib/mmio.h> 12 13 #include <plat_imx8.h> 14 #include <xrdc.h> 15 16 #define PCC_PR BIT(31) 17 #define PFD_VALID_MASK U(0x40404040) 18 19 #define S400_MU_BASE U(0x27020000) 20 #define S400_MU_RSR (S400_MU_BASE + 0x12c) 21 #define S400_MU_TRx(i) (S400_MU_BASE + 0x200 + (i) * 4) 22 #define S400_MU_RRx(i) (S400_MU_BASE + 0x280 + (i) * 4) 23 24 /* 25 * need to re-init the PLL, CGC1, PCC, CMC, XRDC, SIM, GPIO etc. 26 * init the PLL &PFD first, then switch the CA35 clock to PLL for 27 * performance consideration, restore other bus fabric clock. 28 */ 29 30 extern void imx8ulp_caam_init(void); 31 extern void upower_wait_resp(void); 32 extern void dram_enter_retention(void); 33 extern void dram_exit_retention(void); 34 35 struct plat_gic_ctx imx_gicv3_ctx; 36 static uint32_t cmc1_pmprot; 37 static uint32_t cmc1_srie; 38 39 /* TPM5: global timer */ 40 static uint32_t tpm5[3]; 41 42 static uint32_t wdog3[2]; 43 44 /* CGC1 PLL2 */ 45 uint32_t pll2[][2] = { 46 {0x292c0510, 0x0}, {0x292c0518, 0x0}, {0x292c051c, 0x0}, 47 {0x292c0520, 0x0}, {0x292c0500, 0x0}, 48 }; 49 50 /* CGC1 PLL3 */ 51 uint32_t pll3[][2] = { 52 {0x292c0604, 0x0}, {0x292c0608, 0x0}, {0x292c060c, 0x0}, 53 {0x292c0610, 0x0}, {0x292c0618, 0x0}, {0x292c061c, 0x0}, 54 {0x292c0620, 0x0}, {0x292c0624, 0x0}, {0x292c0600, 0x0}, 55 {0x292c0614, 0x0}, 56 }; 57 58 /* CGC1 others */ 59 uint32_t cgc1[][2] = { 60 {0x292c0014, 0x0}, {0x292c0034, 0x0}, {0x292c0038, 0x0}, 61 {0x292c0108, 0x0}, {0x292c0208, 0x0}, {0x292c0700, 0x0}, 62 {0x292c0810, 0x0}, {0x292c0900, 0x0}, {0x292c0904, 0x0}, 63 {0x292c0908, 0x0}, {0x292c090c, 0x0}, {0x292c0a00, 0x0}, 64 }; 65 66 static uint32_t pcc3[61]; 67 static uint32_t pcc4[32]; 68 69 static uint32_t pcc5_0[33]; 70 static uint32_t pcc5_1[][2] = { 71 {0x2da70084, 0x0}, {0x2da70088, 0x0}, {0x2da7008c, 0x0}, 72 {0x2da700a0, 0x0}, {0x2da700a4, 0x0}, {0x2da700a8, 0x0}, 73 {0x2da700ac, 0x0}, {0x2da700b0, 0x0}, {0x2da700b4, 0x0}, 74 {0x2da700bc, 0x0}, {0x2da700c0, 0x0}, {0x2da700c8, 0x0}, 75 {0x2da700cc, 0x0}, {0x2da700d0, 0x0}, {0x2da700f0, 0x0}, 76 {0x2da700f4, 0x0}, {0x2da700f8, 0x0}, {0x2da70108, 0x0}, 77 {0x2da7010c, 0x0}, {0x2da70110, 0x0}, {0x2da70114, 0x0}, 78 }; 79 80 static uint32_t cgc2[][2] = { 81 {0x2da60014, 0x0}, {0x2da60020, 0x0}, {0x2da6003c, 0x0}, 82 {0x2da60040, 0x0}, {0x2da60108, 0x0}, {0x2da60208, 0x0}, 83 {0x2da60900, 0x0}, {0x2da60904, 0x0}, {0x2da60908, 0x0}, 84 {0x2da60910, 0x0}, {0x2da60a00, 0x0}, 85 }; 86 87 static uint32_t pll4[][2] = { 88 {0x2da60604, 0x0}, {0x2da60608, 0x0}, {0x2da6060c, 0x0}, 89 {0x2da60610, 0x0}, {0x2da60618, 0x0}, {0x2da6061c, 0x0}, 90 {0x2da60620, 0x0}, {0x2da60624, 0x0}, {0x2da60600, 0x0}, 91 {0x2da60614, 0x0}, 92 }; 93 94 static uint32_t lpav_sim[][2] = { 95 {0x2da50000, 0x0}, {0x2da50004, 0x0}, {0x2da50008, 0x0}, 96 {0x2da5001c, 0x0}, {0x2da50020, 0x0}, {0x2da50024, 0x0}, 97 {0x2da50034, 0x0}, 98 }; 99 100 #define APD_GPIO_CTRL_NUM 2 101 #define LPAV_GPIO_CTRL_NUM 1 102 #define GPIO_CTRL_REG_NUM 8 103 #define GPIO_PIN_MAX_NUM 32 104 #define GPIO_CTX(addr, num) \ 105 {.base = (addr), .pin_num = (num), } 106 107 struct gpio_ctx { 108 /* gpio base */ 109 uintptr_t base; 110 /* port control */ 111 uint32_t port_ctrl[GPIO_CTRL_REG_NUM]; 112 /* GPIO ICR, Max 32 */ 113 uint32_t pin_num; 114 uint32_t gpio_icr[GPIO_PIN_MAX_NUM]; 115 }; 116 117 static uint32_t gpio_ctrl_offset[GPIO_CTRL_REG_NUM] = { 118 0xc, 0x10, 0x14, 0x18, 0x1c, 0x40, 0x54, 0x58 119 }; 120 static struct gpio_ctx apd_gpio_ctx[APD_GPIO_CTRL_NUM] = { 121 GPIO_CTX(IMX_GPIOE_BASE, 24), 122 GPIO_CTX(IMX_GPIOF_BASE, 32), 123 }; 124 125 static struct gpio_ctx lpav_gpio_ctx = GPIO_CTX(IMX_GPIOD_BASE, 24); 126 /* iomuxc setting */ 127 #define IOMUXC_SECTION_NUM 8 128 struct iomuxc_section { 129 uint32_t offset; 130 uint32_t reg_num; 131 }; 132 133 struct iomuxc_section iomuxc_sections[IOMUXC_SECTION_NUM] = { 134 {.offset = IOMUXC_PTD_PCR_BASE, .reg_num = 24}, 135 {.offset = IOMUXC_PTE_PCR_BASE, .reg_num = 24}, 136 {.offset = IOMUXC_PTF_PCR_BASE, .reg_num = 32}, 137 {.offset = IOMUXC_PSMI_BASE0, .reg_num = 10}, 138 {.offset = IOMUXC_PSMI_BASE1, .reg_num = 61}, 139 {.offset = IOMUXC_PSMI_BASE2, .reg_num = 12}, 140 {.offset = IOMUXC_PSMI_BASE3, .reg_num = 20}, 141 {.offset = IOMUXC_PSMI_BASE4, .reg_num = 75}, 142 }; 143 static uint32_t iomuxc_ctx[258]; 144 145 #define PORTS_NUM 3U 146 void apd_io_pad_off(void) 147 { 148 unsigned int i, j; 149 150 /* off the PTD/E/F, need to be customized based on actual user case */ 151 for (i = 0; i < PORTS_NUM; i++) { 152 for (j = 0; j < iomuxc_sections[i].reg_num; j++) { 153 mmio_write_32(iomuxc_sections[i].offset + j * 4, 0); 154 } 155 } 156 157 /* disable the PTD compensation */ 158 mmio_write_32(IMX_SIM1_BASE + 0x48, 0x800); 159 } 160 161 void iomuxc_save(void) 162 { 163 unsigned int i, j; 164 unsigned int index = 0U; 165 166 for (i = 0U; i < IOMUXC_SECTION_NUM; i++) { 167 for (j = 0U; j < iomuxc_sections[i].reg_num; j++) { 168 iomuxc_ctx[index++] = mmio_read_32(iomuxc_sections[i].offset + j * 4); 169 } 170 } 171 172 apd_io_pad_off(); 173 } 174 175 void iomuxc_restore(void) 176 { 177 unsigned int i, j; 178 unsigned int index = 0U; 179 180 for (i = 0U; i < IOMUXC_SECTION_NUM; i++) { 181 for (j = 0U; j < iomuxc_sections[i].reg_num; j++) { 182 mmio_write_32(iomuxc_sections[i].offset + j * 4, iomuxc_ctx[index++]); 183 } 184 } 185 } 186 187 void gpio_save(struct gpio_ctx *ctx, int port_num) 188 { 189 unsigned int i, j; 190 191 for (i = 0U; i < port_num; i++) { 192 /* save the port control setting */ 193 for (j = 0U; j < GPIO_CTRL_REG_NUM; j++) { 194 if (j < 4U) { 195 ctx->port_ctrl[j] = mmio_read_32(ctx->base + gpio_ctrl_offset[j]); 196 /* 197 * clear the permission setting to read the GPIO 198 * non-secure world setting. 199 */ 200 mmio_write_32(ctx->base + gpio_ctrl_offset[j], 0x0); 201 } else { 202 ctx->port_ctrl[j] = mmio_read_32(ctx->base + gpio_ctrl_offset[j]); 203 } 204 } 205 /* save the gpio icr setting */ 206 for (j = 0U; j < ctx->pin_num; j++) { 207 ctx->gpio_icr[j] = mmio_read_32(ctx->base + 0x80 + j * 4); 208 } 209 210 ctx++; 211 } 212 } 213 214 void gpio_restore(struct gpio_ctx *ctx, int port_num) 215 { 216 unsigned int i, j; 217 218 for (i = 0U; i < port_num; i++) { 219 for (j = 0U; j < ctx->pin_num; j++) 220 mmio_write_32(ctx->base + 0x80 + j * 4, ctx->gpio_icr[j]); 221 222 for (j = 4U; j < GPIO_CTRL_REG_NUM; j++) { 223 mmio_write_32(ctx->base + gpio_ctrl_offset[j], ctx->port_ctrl[j]); 224 } 225 226 /* permission config retore last */ 227 for (j = 0U; j < 4; j++) { 228 mmio_write_32(ctx->base + gpio_ctrl_offset[j], ctx->port_ctrl[j]); 229 } 230 231 ctx++; 232 } 233 } 234 235 void cgc1_save(void) 236 { 237 unsigned int i; 238 239 /* PLL2 */ 240 for (i = 0U; i < ARRAY_SIZE(pll2); i++) { 241 pll2[i][1] = mmio_read_32(pll2[i][0]); 242 } 243 244 /* PLL3 */ 245 for (i = 0U; i < ARRAY_SIZE(pll3); i++) { 246 pll3[i][1] = mmio_read_32(pll3[i][0]); 247 } 248 249 /* CGC1 others */ 250 for (i = 0U; i < ARRAY_SIZE(cgc1); i++) { 251 cgc1[i][1] = mmio_read_32(cgc1[i][0]); 252 } 253 } 254 255 void cgc1_restore(void) 256 { 257 unsigned int i; 258 259 /* PLL2 */ 260 for (i = 0U; i < ARRAY_SIZE(pll2); i++) { 261 mmio_write_32(pll2[i][0], pll2[i][1]); 262 } 263 /* wait for PLL2 lock */ 264 while (!(mmio_read_32(pll2[4][0]) & BIT(24))) { 265 ; 266 } 267 268 /* PLL3 */ 269 for (i = 0U; i < 9U; i++) { 270 mmio_write_32(pll3[i][0], pll3[i][1]); 271 } 272 273 /* wait for PLL3 lock */ 274 while (!(mmio_read_32(pll3[4][0]) & BIT(24))) { 275 ; 276 } 277 278 /* restore the PFDs */ 279 mmio_write_32(pll3[9][0], pll3[9][1] & ~(BIT(31) | BIT(23) | BIT(15) | BIT(7))); 280 mmio_write_32(pll3[9][0], pll3[9][1]); 281 282 /* wait for the PFD is stable, only need to check the enabled PFDs */ 283 while (!(mmio_read_32(pll3[9][0]) & PFD_VALID_MASK)) { 284 ; 285 } 286 287 /* CGC1 others */ 288 for (i = 0U; i < ARRAY_SIZE(cgc1); i++) { 289 mmio_write_32(cgc1[i][0], cgc1[i][1]); 290 } 291 } 292 293 void tpm5_save(void) 294 { 295 tpm5[0] = mmio_read_32(IMX_TPM5_BASE + 0x10); 296 tpm5[1] = mmio_read_32(IMX_TPM5_BASE + 0x18); 297 tpm5[2] = mmio_read_32(IMX_TPM5_BASE + 0x20); 298 } 299 300 void tpm5_restore(void) 301 { 302 mmio_write_32(IMX_TPM5_BASE + 0x10, tpm5[0]); 303 mmio_write_32(IMX_TPM5_BASE + 0x18, tpm5[1]); 304 mmio_write_32(IMX_TPM5_BASE + 0x20, tpm5[2]); 305 } 306 307 void wdog3_save(void) 308 { 309 /* enable wdog3 clock */ 310 mmio_write_32(IMX_PCC3_BASE + 0xa8, 0xd2800000); 311 312 /* save the CS & TOVAL regiter */ 313 wdog3[0] = mmio_read_32(IMX_WDOG3_BASE); 314 wdog3[1] = mmio_read_32(IMX_WDOG3_BASE + 0x8); 315 } 316 317 void wdog3_restore(void) 318 { 319 /* enable wdog3 clock */ 320 mmio_write_32(IMX_PCC3_BASE + 0xa8, 0xd2800000); 321 322 /* reconfig the CS */ 323 mmio_write_32(IMX_WDOG3_BASE, wdog3[0]); 324 /* set the tiemout value */ 325 mmio_write_32(IMX_WDOG3_BASE + 0x8, wdog3[1]); 326 327 /* wait for the lock status */ 328 while ((mmio_read_32(IMX_WDOG3_BASE) & BIT(11))) { 329 ; 330 } 331 332 /* wait for the config done */ 333 while (!(mmio_read_32(IMX_WDOG3_BASE) & BIT(10))) { 334 ; 335 } 336 } 337 338 static uint32_t lpuart_regs[4]; 339 #define LPUART_BAUD 0x10 340 #define LPUART_CTRL 0x18 341 #define LPUART_FIFO 0x28 342 #define LPUART_WATER 0x2c 343 344 void lpuart_save(void) 345 { 346 lpuart_regs[0] = mmio_read_32(IMX_LPUART5_BASE + LPUART_BAUD); 347 lpuart_regs[1] = mmio_read_32(IMX_LPUART5_BASE + LPUART_FIFO); 348 lpuart_regs[2] = mmio_read_32(IMX_LPUART5_BASE + LPUART_WATER); 349 lpuart_regs[3] = mmio_read_32(IMX_LPUART5_BASE + LPUART_CTRL); 350 } 351 352 void lpuart_restore(void) 353 { 354 mmio_write_32(IMX_LPUART5_BASE + LPUART_BAUD, lpuart_regs[0]); 355 mmio_write_32(IMX_LPUART5_BASE + LPUART_FIFO, lpuart_regs[1]); 356 mmio_write_32(IMX_LPUART5_BASE + LPUART_WATER, lpuart_regs[2]); 357 mmio_write_32(IMX_LPUART5_BASE + LPUART_CTRL, lpuart_regs[3]); 358 } 359 360 bool is_lpav_owned_by_apd(void) 361 { 362 return (mmio_read_32(0x2802b044) & BIT(7)) ? true : false; 363 } 364 365 void lpav_ctx_save(void) 366 { 367 unsigned int i; 368 uint32_t val; 369 370 /* CGC2 save */ 371 for (i = 0U; i < ARRAY_SIZE(cgc2); i++) { 372 cgc2[i][1] = mmio_read_32(cgc2[i][0]); 373 } 374 375 /* PLL4 */ 376 for (i = 0U; i < ARRAY_SIZE(pll4); i++) { 377 pll4[i][1] = mmio_read_32(pll4[i][0]); 378 } 379 380 /* PCC5 save */ 381 for (i = 0U; i < ARRAY_SIZE(pcc5_0); i++) { 382 val = mmio_read_32(IMX_PCC5_BASE + i * 4); 383 if (val & PCC_PR) { 384 pcc5_0[i] = val; 385 } 386 } 387 388 for (i = 0U; i < ARRAY_SIZE(pcc5_1); i++) { 389 val = mmio_read_32(pcc5_1[i][0]); 390 if (val & PCC_PR) { 391 pcc5_1[i][1] = val; 392 } 393 } 394 395 /* LPAV SIM save */ 396 for (i = 0U; i < ARRAY_SIZE(lpav_sim); i++) { 397 lpav_sim[i][1] = mmio_read_32(lpav_sim[i][0]); 398 } 399 400 /* Save GPIO port D */ 401 gpio_save(&lpav_gpio_ctx, LPAV_GPIO_CTRL_NUM); 402 403 /* put DDR into retention */ 404 dram_enter_retention(); 405 } 406 407 void lpav_ctx_restore(void) 408 { 409 unsigned int i; 410 411 /* PLL4 */ 412 for (i = 0U; i < 9U; i++) { 413 mmio_write_32(pll4[i][0], pll4[i][1]); 414 } 415 416 /* wait for PLL4 lock */ 417 while (!(mmio_read_32(pll4[8][0]) & BIT(24))) { 418 ; 419 } 420 421 /* restore the PLL4 PFDs */ 422 mmio_write_32(pll4[9][0], pll4[9][1] & ~(BIT(31) | BIT(23) | BIT(15) | BIT(7))); 423 mmio_write_32(pll4[9][0], pll4[9][1]); 424 425 /* wait for the PFD is stable */ 426 while (!(mmio_read_32(pll4[9][0]) & PFD_VALID_MASK)) { 427 ; 428 } 429 430 /* CGC2 restore */ 431 for (i = 0U; i < ARRAY_SIZE(cgc2); i++) { 432 mmio_write_32(cgc2[i][0], cgc2[i][1]); 433 } 434 435 /* PCC5 restore */ 436 for (i = 0U; i < ARRAY_SIZE(pcc5_0); i++) { 437 if (pcc5_0[i] & PCC_PR) { 438 mmio_write_32(IMX_PCC5_BASE + i * 4, pcc5_0[i]); 439 } 440 } 441 442 for (i = 0U; i < ARRAY_SIZE(pcc5_1); i++) { 443 if (pcc5_1[i][1] & PCC_PR) { 444 mmio_write_32(pcc5_1[i][0], pcc5_1[i][1]); 445 } 446 } 447 448 /* LPAV_SIM */ 449 for (i = 0U; i < ARRAY_SIZE(lpav_sim); i++) { 450 mmio_write_32(lpav_sim[i][0], lpav_sim[i][1]); 451 } 452 453 gpio_restore(&lpav_gpio_ctx, LPAV_GPIO_CTRL_NUM); 454 /* DDR retention exit */ 455 dram_exit_retention(); 456 } 457 458 void imx_apd_ctx_save(unsigned int proc_num) 459 { 460 unsigned int i; 461 uint32_t val; 462 463 /* enable LPUART5's clock by default */ 464 mmio_setbits_32(IMX_PCC3_BASE + 0xe8, BIT(30)); 465 466 /* save the gic config */ 467 plat_gic_save(proc_num, &imx_gicv3_ctx); 468 469 cmc1_pmprot = mmio_read_32(IMX_CMC1_BASE + 0x18); 470 cmc1_srie = mmio_read_32(IMX_CMC1_BASE + 0x8c); 471 472 /* save the PCC3 */ 473 for (i = 0U; i < ARRAY_SIZE(pcc3); i++) { 474 /* save the pcc if it is exist */ 475 val = mmio_read_32(IMX_PCC3_BASE + i * 4); 476 if (val & PCC_PR) { 477 pcc3[i] = val; 478 } 479 } 480 481 /* save the PCC4 */ 482 for (i = 0U; i < ARRAY_SIZE(pcc4); i++) { 483 /* save the pcc if it is exist */ 484 val = mmio_read_32(IMX_PCC4_BASE + i * 4); 485 if (val & PCC_PR) { 486 pcc4[i] = val; 487 } 488 } 489 490 /* save the CGC1 */ 491 cgc1_save(); 492 493 wdog3_save(); 494 495 gpio_save(apd_gpio_ctx, APD_GPIO_CTRL_NUM); 496 497 iomuxc_save(); 498 499 tpm5_save(); 500 501 lpuart_save(); 502 503 /* 504 * save the lpav ctx & put the ddr into retention 505 * if lpav master is assigned to APD domain. 506 */ 507 if (is_lpav_owned_by_apd()) { 508 lpav_ctx_save(); 509 } 510 } 511 512 void xrdc_reinit(void) 513 { 514 xrdc_apply_apd_config(); 515 xrdc_apply_lpav_config(); 516 517 xrdc_enable(); 518 } 519 520 void s400_release_caam(void) 521 { 522 uint32_t msg, resp; 523 524 mmio_write_32(S400_MU_TRx(0), 0x17d70206); 525 mmio_write_32(S400_MU_TRx(1), 0x7); 526 527 do { 528 resp = mmio_read_32(S400_MU_RSR); 529 } while ((resp & 0x3) != 0x3); 530 531 msg = mmio_read_32(S400_MU_RRx(0)); 532 resp = mmio_read_32(S400_MU_RRx(1)); 533 534 VERBOSE("resp %x; %x", msg, resp); 535 } 536 537 void imx_apd_ctx_restore(unsigned int proc_num) 538 { 539 unsigned int i; 540 541 /* restore the CCG1 */ 542 cgc1_restore(); 543 544 for (i = 0U; i < ARRAY_SIZE(pcc3); i++) { 545 /* save the pcc if it is exist */ 546 if (pcc3[i] & PCC_PR) { 547 mmio_write_32(IMX_PCC3_BASE + i * 4, pcc3[i]); 548 } 549 } 550 551 for (i = 0U; i < ARRAY_SIZE(pcc4); i++) { 552 if (pcc4[i] & PCC_PR) { 553 mmio_write_32(IMX_PCC4_BASE + i * 4, pcc4[i]); 554 } 555 } 556 557 wdog3_restore(); 558 559 iomuxc_restore(); 560 561 tpm5_restore(); 562 563 xrdc_reinit(); 564 565 /* Restore GPIO after xrdc_reinit, otherwise MSCs are invalid */ 566 gpio_restore(apd_gpio_ctx, APD_GPIO_CTRL_NUM); 567 568 /* restore the gic config */ 569 plat_gic_restore(proc_num, &imx_gicv3_ctx); 570 571 mmio_write_32(IMX_CMC1_BASE + 0x18, cmc1_pmprot); 572 mmio_write_32(IMX_CMC1_BASE + 0x8c, cmc1_srie); 573 574 /* enable LPUART5's clock by default */ 575 mmio_setbits_32(IMX_PCC3_BASE + 0xe8, BIT(30)); 576 577 /* restore the console lpuart */ 578 lpuart_restore(); 579 580 /* FIXME: make uart work for ATF */ 581 mmio_write_32(IMX_LPUART_BASE + 0x18, 0xc0000); 582 583 /* Allow M core to reset A core */ 584 mmio_clrbits_32(IMX_MU0B_BASE + 0x10, BIT(2)); 585 /* 586 * Ask S400 to release caam to APD as it is owned by s400 587 */ 588 s400_release_caam(); 589 590 /* re-init the caam */ 591 imx8ulp_caam_init(); 592 593 /* 594 * ack the upower, seems a necessary steps, otherwise the upower can 595 * not response to the new API service call. put this just before the 596 * ddr retention exit because that the dram retention exit flow need to 597 * communicate with upower. 598 */ 599 upower_wait_resp(); 600 601 /* 602 * restore the lpav ctx & make ddr out of retention 603 * if lpav master is assigned to APD domain. 604 */ 605 if (is_lpav_owned_by_apd()) { 606 lpav_ctx_restore(); 607 } 608 } 609 610 #define DGO_CTRL1 U(0xc) 611 #define USB_WAKEUP U(0x44) 612 #define USB1_PHY_DPD_WAKEUP_EN BIT_32(5) 613 #define USB0_PHY_DPD_WAKEUP_EN BIT_32(4) 614 #define USB1_PHY_WAKEUP_ISO_DISABLE BIT_32(1) 615 #define USB0_PHY_WAKEUP_ISO_DISABLE BIT_32(0) 616 617 void usb_wakeup_enable(bool enable) 618 { 619 if (enable) { 620 mmio_setbits_32(IMX_SIM1_BASE + USB_WAKEUP, 621 USB1_PHY_WAKEUP_ISO_DISABLE | USB0_PHY_WAKEUP_ISO_DISABLE); 622 mmio_setbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); 623 while (!(mmio_read_32(IMX_SIM1_BASE + DGO_CTRL1) & BIT(1))) { 624 ; 625 } 626 627 mmio_clrbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); 628 mmio_write_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(1)); 629 630 /* Need to delay for a while to make sure the wakeup logic can work */ 631 udelay(500); 632 633 mmio_setbits_32(IMX_SIM1_BASE + USB_WAKEUP, 634 USB1_PHY_DPD_WAKEUP_EN | USB0_PHY_DPD_WAKEUP_EN); 635 mmio_setbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); 636 while (!(mmio_read_32(IMX_SIM1_BASE + DGO_CTRL1) & BIT(1))) { 637 ; 638 } 639 640 mmio_clrbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); 641 mmio_write_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(1)); 642 } else { 643 /* 644 * USBx_PHY_DPD_WAKEUP_EN should be cleared before USB0_PHY_WAKEUP_ISO_DISABLE 645 * to provide the correct the wake-up functionality. 646 */ 647 mmio_write_32(IMX_SIM1_BASE + USB_WAKEUP, USB1_PHY_WAKEUP_ISO_DISABLE | 648 USB0_PHY_WAKEUP_ISO_DISABLE); 649 mmio_write_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); 650 while (!(mmio_read_32(IMX_SIM1_BASE + DGO_CTRL1) & BIT(1))) { 651 ; 652 } 653 654 mmio_clrbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); 655 mmio_write_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(1)); 656 } 657 } 658