1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 12 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 13 #define PLATFORM_LINKER_ARCH aarch64 14 15 #define PLATFORM_STACK_SIZE 0x400 16 #define CACHE_WRITEBACK_GRANULE 64 17 18 #define PLAT_PRIMARY_CPU U(0x0) 19 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4) 20 #define PLATFORM_CLUSTER_COUNT U(1) 21 #define PLATFORM_CORE_COUNT U(4) 22 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 23 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 24 25 #define PWR_DOMAIN_AT_MAX_LVL U(1) 26 #define PLAT_MAX_PWR_LVL U(2) 27 #define PLAT_MAX_OFF_STATE U(2) 28 #define PLAT_MAX_RET_STATE U(1) 29 30 #define BL31_BASE 0x80000000 31 #define BL31_LIMIT 0x80020000 32 33 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 34 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 35 36 #define MAX_XLAT_TABLES 8 37 #define MAX_MMAP_REGIONS 8 38 39 #define PLAT_GICD_BASE 0x51a00000 40 #define PLAT_GICR_BASE 0x51b00000 41 #define IMX_BOOT_UART_BASE 0x5a060000 42 #define IMX_BOOT_UART_BAUDRATE 115200 43 #define IMX_BOOT_UART_CLK_IN_HZ 24000000 44 #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 45 #define PLAT__CRASH_UART_CLK_IN_HZ 24000000 46 #define IMX_CONSOLE_BAUDRATE 115200 47 #define SC_IPC_BASE 0x5d1b0000 48 #define IMX_GPT0_LPCG_BASE 0x5d540000 49 #define IMX_GPT0_BASE 0x5d140000 50 #define IMX_WUP_IRQSTR_BASE 0x51090000 51 #define IMX_REG_BASE 0x50000000 52 #define IMX_REG_SIZE 0x10000000 53 54 #define COUNTER_FREQUENCY 8000000 55 56 /* non-secure u-boot base */ 57 #define PLAT_NS_IMAGE_OFFSET 0x80020000 58 59 #define DEBUG_CONSOLE 0 60 #define DEBUG_CONSOLE_A35 0 61 62 #endif /* PLATFORM_DEF_H */ 63