10bc18309SAnson Huang /* 20bc18309SAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 30bc18309SAnson Huang * 40bc18309SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 50bc18309SAnson Huang */ 60bc18309SAnson Huang 71083b2b3SAntonio Nino Diaz #ifndef PLATFORM_DEF_H 81083b2b3SAntonio Nino Diaz #define PLATFORM_DEF_H 91083b2b3SAntonio Nino Diaz 1009d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 110bc18309SAnson Huang 120bc18309SAnson Huang #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 130bc18309SAnson Huang #define PLATFORM_LINKER_ARCH aarch64 140bc18309SAnson Huang 150bc18309SAnson Huang #define PLATFORM_STACK_SIZE 0x400 160bc18309SAnson Huang #define CACHE_WRITEBACK_GRANULE 64 170bc18309SAnson Huang 180bc18309SAnson Huang #define PLAT_PRIMARY_CPU 0x0 190bc18309SAnson Huang #define PLATFORM_MAX_CPU_PER_CLUSTER 4 200bc18309SAnson Huang #define PLATFORM_CLUSTER_COUNT 1 210bc18309SAnson Huang #define PLATFORM_CORE_COUNT 4 220f53bca0SAnson Huang #define PLATFORM_CLUSTER0_CORE_COUNT 4 230f53bca0SAnson Huang #define PLATFORM_CLUSTER1_CORE_COUNT 0 240bc18309SAnson Huang 251083b2b3SAntonio Nino Diaz #define PWR_DOMAIN_AT_MAX_LVL U(1) 261083b2b3SAntonio Nino Diaz #define PLAT_MAX_PWR_LVL U(2) 271083b2b3SAntonio Nino Diaz #define PLAT_MAX_OFF_STATE U(2) 281083b2b3SAntonio Nino Diaz #define PLAT_MAX_RET_STATE U(1) 290bc18309SAnson Huang 300bc18309SAnson Huang #define BL31_BASE 0x80000000 310bc18309SAnson Huang #define BL31_LIMIT 0x80020000 320bc18309SAnson Huang 330bc18309SAnson Huang #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 340bc18309SAnson Huang #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 350bc18309SAnson Huang 360bc18309SAnson Huang #define MAX_XLAT_TABLES 8 370bc18309SAnson Huang #define MAX_MMAP_REGIONS 8 380bc18309SAnson Huang 390bc18309SAnson Huang #define PLAT_GICD_BASE 0x51a00000 400bc18309SAnson Huang #define PLAT_GICR_BASE 0x51b00000 410bc18309SAnson Huang #define IMX_BOOT_UART_BASE 0x5a060000 420bc18309SAnson Huang #define IMX_BOOT_UART_BAUDRATE 115200 430bc18309SAnson Huang #define IMX_BOOT_UART_CLK_IN_HZ 24000000 440bc18309SAnson Huang #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 450bc18309SAnson Huang #define PLAT__CRASH_UART_CLK_IN_HZ 24000000 460bc18309SAnson Huang #define IMX_CONSOLE_BAUDRATE 115200 470bc18309SAnson Huang #define SC_IPC_BASE 0x5d1b0000 48*e6cf7a46SAnson Huang #define IMX_GPT0_LPCG_BASE 0x5d540000 49*e6cf7a46SAnson Huang #define IMX_GPT0_BASE 0x5d140000 50*e6cf7a46SAnson Huang #define IMX_WUP_IRQSTR_BASE 0x51090000 51*e6cf7a46SAnson Huang #define IMX_REG_BASE 0x50000000 52*e6cf7a46SAnson Huang #define IMX_REG_SIZE 0x10000000 530bc18309SAnson Huang 540bc18309SAnson Huang #define COUNTER_FREQUENCY 8000000 550bc18309SAnson Huang 560bc18309SAnson Huang /* non-secure u-boot base */ 570bc18309SAnson Huang #define PLAT_NS_IMAGE_OFFSET 0x80020000 580bc18309SAnson Huang 590bc18309SAnson Huang #define DEBUG_CONSOLE 0 600bc18309SAnson Huang #define DEBUG_CONSOLE_A35 0 610bc18309SAnson Huang #define PLAT_IMX8QX 1 620bc18309SAnson Huang 631083b2b3SAntonio Nino Diaz #endif /* PLATFORM_DEF_H */ 64