10bc18309SAnson Huang /* 20bc18309SAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 30bc18309SAnson Huang * 40bc18309SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 50bc18309SAnson Huang */ 60bc18309SAnson Huang 70bc18309SAnson Huang #ifndef __PLATFORM_DEF_H__ 80bc18309SAnson Huang #define __PLATFORM_DEF_H__ 90bc18309SAnson Huang 100bc18309SAnson Huang #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 110bc18309SAnson Huang #define PLATFORM_LINKER_ARCH aarch64 120bc18309SAnson Huang 130bc18309SAnson Huang #define PLATFORM_STACK_SIZE 0x400 140bc18309SAnson Huang #define CACHE_WRITEBACK_GRANULE 64 150bc18309SAnson Huang 160bc18309SAnson Huang #define PLAT_PRIMARY_CPU 0x0 170bc18309SAnson Huang #define PLATFORM_MAX_CPU_PER_CLUSTER 4 180bc18309SAnson Huang #define PLATFORM_CLUSTER_COUNT 1 190bc18309SAnson Huang #define PLATFORM_CORE_COUNT 4 20*0f53bca0SAnson Huang #define PLATFORM_CLUSTER0_CORE_COUNT 4 21*0f53bca0SAnson Huang #define PLATFORM_CLUSTER1_CORE_COUNT 0 220bc18309SAnson Huang 230bc18309SAnson Huang #define PWR_DOMAIN_AT_MAX_LVL 1 240bc18309SAnson Huang #define PLAT_MAX_PWR_LVL 2 250bc18309SAnson Huang #define PLAT_MAX_OFF_STATE 2 260bc18309SAnson Huang #define PLAT_MAX_RET_STATE 1 270bc18309SAnson Huang 280bc18309SAnson Huang #define BL31_BASE 0x80000000 290bc18309SAnson Huang #define BL31_LIMIT 0x80020000 300bc18309SAnson Huang 310bc18309SAnson Huang #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 320bc18309SAnson Huang #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 330bc18309SAnson Huang 340bc18309SAnson Huang #define MAX_XLAT_TABLES 8 350bc18309SAnson Huang #define MAX_MMAP_REGIONS 8 360bc18309SAnson Huang 370bc18309SAnson Huang #define PLAT_GICD_BASE 0x51a00000 380bc18309SAnson Huang #define PLAT_GICD_SIZE 0x10000 390bc18309SAnson Huang #define PLAT_GICR_BASE 0x51b00000 400bc18309SAnson Huang #define PLAT_GICR_SIZE 0xc0000 410bc18309SAnson Huang #define IMX_BOOT_UART_BASE 0x5a060000 420bc18309SAnson Huang #define IMX_BOOT_UART_SIZE 0x1000 430bc18309SAnson Huang #define IMX_BOOT_UART_BAUDRATE 115200 440bc18309SAnson Huang #define IMX_BOOT_UART_CLK_IN_HZ 24000000 450bc18309SAnson Huang #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 460bc18309SAnson Huang #define PLAT__CRASH_UART_CLK_IN_HZ 24000000 470bc18309SAnson Huang #define IMX_CONSOLE_BAUDRATE 115200 480bc18309SAnson Huang #define SC_IPC_BASE 0x5d1b0000 490bc18309SAnson Huang #define SC_IPC_SIZE 0x10000 500bc18309SAnson Huang 510bc18309SAnson Huang #define COUNTER_FREQUENCY 8000000 520bc18309SAnson Huang 530bc18309SAnson Huang /* non-secure u-boot base */ 540bc18309SAnson Huang #define PLAT_NS_IMAGE_OFFSET 0x80020000 550bc18309SAnson Huang 560bc18309SAnson Huang #define DEBUG_CONSOLE 0 570bc18309SAnson Huang #define DEBUG_CONSOLE_A35 0 580bc18309SAnson Huang #define PLAT_IMX8QX 1 590bc18309SAnson Huang 600bc18309SAnson Huang #endif /* __PLATFORM_DEF_H__ */ 61