1*0bc18309SAnson Huang /* 2*0bc18309SAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*0bc18309SAnson Huang * 4*0bc18309SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5*0bc18309SAnson Huang */ 6*0bc18309SAnson Huang 7*0bc18309SAnson Huang #ifndef __PLATFORM_DEF_H__ 8*0bc18309SAnson Huang #define __PLATFORM_DEF_H__ 9*0bc18309SAnson Huang 10*0bc18309SAnson Huang #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 11*0bc18309SAnson Huang #define PLATFORM_LINKER_ARCH aarch64 12*0bc18309SAnson Huang 13*0bc18309SAnson Huang #define PLATFORM_STACK_SIZE 0x400 14*0bc18309SAnson Huang #define CACHE_WRITEBACK_GRANULE 64 15*0bc18309SAnson Huang 16*0bc18309SAnson Huang #define PLAT_PRIMARY_CPU 0x0 17*0bc18309SAnson Huang #define PLATFORM_MAX_CPU_PER_CLUSTER 4 18*0bc18309SAnson Huang #define PLATFORM_CLUSTER_COUNT 1 19*0bc18309SAnson Huang #define PLATFORM_CORE_COUNT 4 20*0bc18309SAnson Huang 21*0bc18309SAnson Huang #define PWR_DOMAIN_AT_MAX_LVL 1 22*0bc18309SAnson Huang #define PLAT_MAX_PWR_LVL 2 23*0bc18309SAnson Huang #define PLAT_MAX_OFF_STATE 2 24*0bc18309SAnson Huang #define PLAT_MAX_RET_STATE 1 25*0bc18309SAnson Huang 26*0bc18309SAnson Huang #define BL31_BASE 0x80000000 27*0bc18309SAnson Huang #define BL31_LIMIT 0x80020000 28*0bc18309SAnson Huang 29*0bc18309SAnson Huang #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 30*0bc18309SAnson Huang #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 31*0bc18309SAnson Huang 32*0bc18309SAnson Huang #define MAX_XLAT_TABLES 8 33*0bc18309SAnson Huang #define MAX_MMAP_REGIONS 8 34*0bc18309SAnson Huang 35*0bc18309SAnson Huang #define PLAT_GICD_BASE 0x51a00000 36*0bc18309SAnson Huang #define PLAT_GICD_SIZE 0x10000 37*0bc18309SAnson Huang #define PLAT_GICR_BASE 0x51b00000 38*0bc18309SAnson Huang #define PLAT_GICR_SIZE 0xc0000 39*0bc18309SAnson Huang #define IMX_BOOT_UART_BASE 0x5a060000 40*0bc18309SAnson Huang #define IMX_BOOT_UART_SIZE 0x1000 41*0bc18309SAnson Huang #define IMX_BOOT_UART_BAUDRATE 115200 42*0bc18309SAnson Huang #define IMX_BOOT_UART_CLK_IN_HZ 24000000 43*0bc18309SAnson Huang #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 44*0bc18309SAnson Huang #define PLAT__CRASH_UART_CLK_IN_HZ 24000000 45*0bc18309SAnson Huang #define IMX_CONSOLE_BAUDRATE 115200 46*0bc18309SAnson Huang #define SC_IPC_BASE 0x5d1b0000 47*0bc18309SAnson Huang #define SC_IPC_SIZE 0x10000 48*0bc18309SAnson Huang 49*0bc18309SAnson Huang #define COUNTER_FREQUENCY 8000000 50*0bc18309SAnson Huang 51*0bc18309SAnson Huang /* non-secure u-boot base */ 52*0bc18309SAnson Huang #define PLAT_NS_IMAGE_OFFSET 0x80020000 53*0bc18309SAnson Huang 54*0bc18309SAnson Huang #define DEBUG_CONSOLE 0 55*0bc18309SAnson Huang #define DEBUG_CONSOLE_A35 0 56*0bc18309SAnson Huang #define PLAT_IMX8QX 1 57*0bc18309SAnson Huang 58*0bc18309SAnson Huang #endif /* __PLATFORM_DEF_H__ */ 59